Kim Lux
Diesel Research Inc.
November 24, 2004
Document Version 0.01: ROUGH DRAFT
The MC9S12DP256 is a paged memory device.
One can think of it as having 2 separate memory systems:
a) a non paged memory bank with addresses from 0x0000 to 0xffff
b) a paged memory bank with addresses from 0x00000 to 0xfffff
When operated in non paged mode, the non paged memory bank is accessible
just like any other 64K linear addressed memory map. In non paged mode
you cannot access any of the paged memory and PPAGE must be kept
stationary at 0x30. (I need to verify this with non far addressing.)
This will yield the following memory map:
0x1000 to 0x3FFF: RAM
0x4000 to 0xFFFF: Flash ROM
Simple, right ?
Lets say that we need more memory than that, so we expand our system
with some external RAM/ROM and start to utilize the rest of the 256K of
flash as well as the RAM/ROM we add. Now things get a bit complicated.
The rest of the flash and the ROM/RAM we added are now accessed through
a 4K section right in the middle of our 64K memory map. This section is
called the page window, because it is the "hole" or "window" through
which we peak to access the paged memory.
The paged memory map looks like this:
0x1000 to 0x3FFF: RAM
0x4000 to 0x7FFF: Flash ROM
0x8000 to 0xBFFF: paged memory window, where we access the paged memory.
0xC000 to 0xFFFF: Flash ROM
PLUS all the paged memory.
Which part of the paged memory shows in the paged memory window ?
The memory that appears in the paged memory window depends on the value
of PPAGE:
0x00 to 0x2F: 1 page of 48 16K pages of externally addressed memory
appears in the window. (768K in total) This could be ROM or RAM or any
external hardware addressable devices that we tie to the 9S12 external
address bus.
0x30 to 0x3F: 1 page of 16 16K pages of on chip flash memory appears in
the window. (256K in total.)
There is one other little tidbit of information you need to know: 2 of
the paged flash pages are shared with the non paged memory.
The flash memory on page 0x3E is the same memory that appears in the non
paged memory map from 0x4000 to ox7FFF.
The flash memory on page 0x3F is the same memory that appears in the non
paged memory map from 0xC000 to 0xFFFF.
The memory in these two overlapping pages can be accessed by either the
non paged access method or the paged access method.
Loading Programs and Data on the 'DP256 via D-BUG12
NOTE: The following discussion assumes a linear load addressing model,
not a banked load addressing model. For further details, consult
Appendix A of the D-Bug12 v4.x.x Reference Guide.
DBUG12 provides 2 commands for loading data onto the DP256: load and
fload.
Between the two commands, all the paged and non paged memory on the
DP256 is accessible for loading.
The "load" command is used to program non flash areas of the DP256. It
can load data into non flash memory located in the non paged or paged
areas.
The "fload" command is used to program the flash areas of the DP256
memory map. It can load data into flash located in the non paged or
paged areas.
Loading Non Flash Areas
To load data into the non paged memory area (non flash) of the DP256,
one issues the command "load" and sends an S1 or S2 file with
appropriately addressed data. Since the only non paged non flash
address area in the DP256 is 0x1000 to 0x4000, this is the only suitable
range of memory that can be loaded this way.
To load data into the paged memory area of the DP256, one issues the
command "load ;f" and sends a file of S2 records with the appropriate
addressing. To simplify the code generation, in linear load addressing
mode, the load command handles the control of the PPAGE register, making
it transparent to the user. To do this, a mapping is used between the
load address used in the SRecords and the ultimate machine address the
data will sit at:
Load Address PPAGE RAM Page
0x00000 to 0x3FFF 0x00 0
0x04000 to 0x7FFF 0x01 1
..
0xB8FFF to 0xBFFFF 0x2F 48
So.. you generate a linear load map and load will take care of putting
your data on the correct page.
To recap loading non flash areas:
"load" loads non flash non paged areas.
"load ;f" loads non flash paged areas.
"load" with records at 0x1000 will load on chip RAM.
'load ;f" with records at 0x1000 will load page 0 of the paged ram.
Loading Flash Memory Areas
To load data into the non paged flash area of the DP256, one issues the
command "fload ;b" and sends an S1 or S2 file with appropriately
addressed data. Since the only non paged flash address area in the
DP256 is 0x4000 to 0x7FFF and 0xC000 to 0xFFFF, these are the only
suitable range of memory that can be loaded this way.
To load data into the paged flash memory area of the DP256, one issues
the command "fload" and sends a file of S2 records with the appropriate
addressing. To simplify the code generation, in linear load addressing
mode, the fload command handles the control of the PPAGE register,
making it transparent to the user. To do this, a mapping is used
between the fload address used in the SRecords and the ultimate machine
address the data will sit at:
fload Address PPAGE Flash Page
0xC0000 to 0xC3FFF 0x30 1
0xC4000 to 0xC7FFF 0x31 2
..
0xFC000 to 0xFFFFF 0x3F 16
So.. you generate a linear load map and fload will take care of putting
your data on the correct page.
To recap loading flash areas:
"load ;b" loads non paged flash areas.
"load" loads paged flash areas.
Remember how the two non paged flash areas overlapped with two of the
paged flash areas ? Ie page 0x3E overlapped with 0x4000 to 0x7FFF and
page 3F overlapped with 0xFC000 to 0xFFFFF ? Well, you can load those
pages by either method.
Accessing The Loaded Data - Manually
The non paged data outside of the page window (0x8000 to 0xBFFF),
including the non paged flash pages, ie 0x4000 to 0x7FFF and 0xC000 to
0xFFFF, is accessed just like any other data with no special care
needed. For example, if you loaded data in flash at location 0x4004,
you could access it with the address 0x4004.
It takes a bit more to access the paged data. The paged data is always
read in the window at 0x8000 to 0xBFFF. What appears in that window
depends on the PPAGE value. For example, to access the second byte of
the first page of paged ram, one would set PPAGE to 0x00 and the data
would then appear at the window base address plus the offset address, ie
0x8000 + 0x01 = 0x8001.
Likewise, to access the second byte of the first page of flash memory,
one would set PPAGE to 0x30 and the data would then appear at the window
base address plus the offset address ie 0x8000 + 0x01 = 0x8001.
Note that in both of these cases the 64K address we are using to access
the data is the same, however the PPAGE controls what we actually get by
controlling the page that appears in the window. (Ie RAM page 0 or flash
page 0 in this case.)
It can get very tiresome thinking of paged memory as being on certain
pages, so code generators generally generate (say that 3x fast...)
linearly addressed data which then allows the user to use a formula to
set PPAGE and the window address:
PPAGE = PagedLoadAddress / PPAGEWindowSize;
and
PageWindowAddress = (PageLoadAddress % PPAGEWindowSize) +
PPAGEWindowStart;
Where:
"/" is integer division
"%" is modulus
PPAGEWindows size = 16K = 0x4000 for the 'DP256
PPAFEWindowStart = 0x8000 for the 'DP256
The above equations work directly as "C" code.
Thus as long as you know where you loaded the data via the linear load
address, you can retreive it quite easily.
Note that this address decoding works with the two pages of paged flash
shared with the non paged memory map. If you stored data at linear load
address 0xF8002, you will be able to retreive it with the above
equations.
Please be aware that the PAGED load addresses are not the same as the
NON PAGED load addresses. PAGED load address 0x1000 will be on the
first page of external memory. NONPAGED load address 0x1000 is the
start of on chip RAM.
As explained previously, the PAGED load address is loaded with "load ;f"
and the NON PAGED load address is loaded with "load".
Using gcc with 'DP256 Paged Addressing
When correctly configured, gcc will generate a linear memory map that
has paged and non paged components. Furthermore, gcc lets the user, via
the "far" keyword, designate where various code and data resides, either
in the non paged "near" areas or in the paged "far" areas.
Fortunately for developers, gcc handles the calculation and setting of
the PPAGE register automatically when accessing "far" data and code.
Using gdb with 'DP256 Paged Addressing
gdb has several tasks with paged and non paged memory implications when
debugging a 'DP256 device:
a) to program data on the DP256 on behalf of the gdb client
b) to read data on the DP256 device on behalf of the gdb client
--
Kim Lux (Mr.) Diesel Research Inc
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