8. Machine Dependent Features

The machine instruction sets are (almost by definition) different on each machine where as runs. Floating point representations vary as well, and as often supports a few additional directives or command-line options for compatibility with other assemblers on a particular platform. Finally, some versions of as support special pseudo-instructions for branch optimization.

This chapter discusses most of these differences, though it does not include details on any machine's instruction set. For details on that subject, see the hardware manufacturer's manual.

8.1 AMD 29K Dependent Features
8.2 Alpha Dependent Features
8.3 ARC Dependent Features
8.4 ARM Dependent Features
8.5 CRIS Dependent Features
8.6 D10V Dependent Features
8.7 D30V Dependent Features
8.8 H8/300 Dependent Features		Renesas H8/300 Dependent Features
8.9 H8/500 Dependent Features		Renesas H8/500 Dependent Features
8.10 HPPA Dependent Features
8.11 ESA/390 Dependent Features		IBM ESA/390 Dependent Features
8.12 80386 Dependent Features		Intel 80386 and AMD x86-64 Dependent Features
8.13 Intel i860 Dependent Features		Intel 80860 Dependent Features
8.14 Intel 80960 Dependent Features
8.15 IP2K Dependent Features
8.16 M32R Dependent Features
8.17 M680x0 Dependent Features
8.18 M68HC11 and M68HC12 Dependent Features		M68HC11 and 68HC12 Dependent Features
8.19 Motorola M88K Dependent Features		M880x0 Dependent Features
8.20 MIPS Dependent Features
8.21 MMIX Dependent Features
8.22 MSP 430 Dependent Features
8.26 Renesas / SuperH SH Dependent Features
8.27 SuperH SH64 Dependent Features
8.23 PDP-11 Dependent Features
8.24 picoJava Dependent Features
8.25 PowerPC Dependent Features
8.28 SPARC Dependent Features
8.29 TIC54X Dependent Features		TI TMS320C54x Dependent Features
8.32 v850 Dependent Features		V850 Dependent Features
8.33 Xtensa Dependent Features
8.30 Z8000 Dependent Features
8.31 VAX Dependent Features

8.1 AMD 29K Dependent Features

8.1.1 Options
8.1.2 Syntax
8.1.3 Floating Point
8.1.4 AMD 29K Machine Directives
8.1.5 Opcodes

8.1.1 Options

8.1.2 Syntax

8.1.2.1 Macros
8.1.2.2 Special Characters
8.1.2.3 Register Names

8.1.2.1 Macros

The macro syntax used on the AMD 29K is like that described in the AMD 29K Family Macro Assembler Specification. Normal as macros should still work.

8.1.2.2 Special Characters

`;' is the line comment character.

The character `?' is permitted in identifiers (but may not begin an identifier).

8.1.2.3 Register Names

General-purpose registers are represented by predefined symbols of the form `GRnnn' (for global registers) or `LRnnn' (for local registers), where nnn represents a number between 0 and 127, written with no leading zeros. The leading letters may be in either upper or lower case; for example, `gr13' and `LR7' are both valid register names.

You may also refer to general-purpose registers by specifying the register number as the result of an expression (prefixed with `%%' to flag the expression as a register number):

%%expression

---where expression must be an absolute expression evaluating to a number between 0 and 255. The range [0, 127] refers to global registers, and the range [128, 255] to local registers.

In addition, as understands the following protected special-purpose register names for the AMD 29K family:

vab chd pc0 ops chc pc1 cps rbp pc2 cfg tmc mmu cha tmr lru

These unprotected special-purpose register names are also recognized:

ipc alu fpe ipa bp inte ipb fc fps q cr exop

8.1.3 Floating Point

The AMD 29K family uses IEEE floating-point numbers.

8.1.4 AMD 29K Machine Directives

.block size , fill

This directive emits size bytes, each of value fill. Both size and fill are absolute expressions. If the comma and fill are omitted, fill is assumed to be zero.

In other versions of the GNU assembler, this directive is called `.space'.

.cputype

This directive is ignored; it is accepted for compatibility with other AMD 29K assemblers.

.file

This directive is ignored; it is accepted for compatibility with other AMD 29K assemblers.

Warning: in other versions of the GNU assembler, .file is used for the directive called .app-file in the AMD 29K support.

.line

This directive is ignored; it is accepted for compatibility with other AMD 29K assemblers.

.sect

This directive is ignored; it is accepted for compatibility with other AMD 29K assemblers.

.use section name

Establishes the section and subsection for the following code; section name may be one of .text, .data, .data1, or .lit. With one of the first three section name options, `.use' is equivalent to the machine directive section name; the remaining case, `.use .lit', is the same as `.data 200'.

8.1.5 Opcodes

as implements all the standard AMD 29K opcodes. No additional pseudo-instructions are needed on this family.

For information on the 29K machine instruction set, see Am29000 User's Manual, Advanced Micro Devices, Inc.

8.2 Alpha Dependent Features

8.2.1 Notes
8.2.2 Options
8.2.3 Syntax
8.2.4 Floating Point
8.2.5 Alpha Assembler Directives		Alpha Machine Directives
8.2.6 Opcodes

8.2.1 Notes

The documentation here is primarily for the ELF object format. as also supports the ECOFF and EVAX formats, but features specific to these formats are not yet documented.

8.2.2 Options

`-mcpu'

This option specifies the target processor. If an attempt is made to assemble an instruction which will not execute on the target processor, the assembler may either expand the instruction as a macro or issue an error message. This option is equivalent to the .arch directive.

The following processor names are recognized: 21064, 21064a, 21066, 21068, 21164, 21164a, 21164pc, 21264, 21264a, 21264b, ev4, ev5, lca45, ev5, ev56, pca56, ev6, ev67, ev68. The special name all may be used to allow the assembler to accept instructions valid for any Alpha processor.

In order to support existing practice in OSF/1 with respect to .arch, and existing practice within MILO (the Linux ARC bootloader), the numbered processor names (e.g. 21064) enable the processor-specific PALcode instructions, while the "electro-vlasic" names (e.g. ev4) do not.

`-mdebug'

`-no-mdebug'

Enables or disables the generation of .mdebug encapsulation for stabs directives and procedure descriptors. The default is to automatically enable .mdebug when the first stabs directive is seen.

`-relax'

This option forces all relocations to be put into the object file, instead of saving space and resolving some relocations at assembly time. Note that this option does not propagate all symbol arithmetic into the object file, because not all symbol arithmetic can be represented. However, the option can still be useful in specific applications.

`-g'

This option is used when the compiler generates debug information. When gcc is using mips-tfile to generate debug information for ECOFF, local labels must be passed through to the object file. Otherwise this option has no effect.

`-Gsize'

A local common symbol larger than size is placed in .bss, while smaller symbols are placed in .sbss.

`-F'

`-32addr'

These options are ignored for backward compatibility.

8.2.3 Syntax

8.2.3.1 Special Characters
8.2.3.2 Register Names
8.2.3.3 Relocations

8.2.3.1 Special Characters

`#' is the line comment character.

`;' can be used instead of a newline to separate statements.

8.2.3.2 Register Names

The 32 integer registers are referred to as `$n' or `$rn'. In addition, registers 15, 28, 29, and 30 may be referred to by the symbols `$fp', `$at', `$gp', and `$sp' respectively.

The 32 floating-point registers are referred to as `$fn'.

8.2.3.3 Relocations

Some of these relocations are available for ECOFF, but mostly only for ELF. They are modeled after the relocation format introduced in Digital Unix 4.0, but there are additions.

The format is `!tag' or `!tag!number' where tag is the name of the relocation. In some cases number is used to relate specific instructions.

The relocation is placed at the end of the instruction like so:

ldah $0,a($29) !gprelhigh lda $0,a($0) !gprellow ldq $1,b($29) !literal!100 ldl $2,0($1) !lituse_base!100

!literal

!literal!N

Used with an ldq instruction to load the address of a symbol from the GOT.

A sequence number N is optional, and if present is used to pair lituse relocations with this literal relocation. The lituse relocations are used by the linker to optimize the code based on the final location of the symbol.

Note that these optimizations are dependent on the data flow of the program. Therefore, if any lituse is paired with a literal relocation, then all uses of the register set by the literal instruction must also be marked with lituse relocations. This is because the original literal instruction may be deleted or transformed into another instruction.

Also note that there may be a one-to-many relationship between literal and lituse, but not a many-to-one. That is, if there are two code paths that load up the same address and feed the value to a single use, then the use may not use a lituse relocation.

!lituse_base!N

Used with any memory format instruction (e.g. ldl) to indicate that the literal is used for an address load. The offset field of the instruction must be zero. During relaxation, the code may be altered to use a gp-relative load.

!lituse_jsr!N

Used with a register branch format instruction (e.g. jsr) to indicate that the literal is used for a call. During relaxation, the code may be altered to use a direct branch (e.g. bsr).

!lituse_bytoff!N

Used with a byte mask instruction (e.g. extbl) to indicate that only the low 3 bits of the address are relevant. During relaxation, the code may be altered to use an immediate instead of a register shift.

!lituse_addr!N

Used with any other instruction to indicate that the original address is in fact used, and the original ldq instruction may not be altered or deleted. This is useful in conjunction with lituse_jsr to test whether a weak symbol is defined.

ldq $27,foo($29) !literal!1 beq $27,is_undef !lituse_addr!1 jsr $26,($27),foo !lituse_jsr!1

!lituse_tlsgd!N

Used with a register branch format instruction to indicate that the literal is the call to __tls_get_addr used to compute the address of the thread-local storage variable whose descriptor was loaded with !tlsgd!N.

!lituse_tlsldm!N

Used with a register branch format instruction to indicate that the literal is the call to __tls_get_addr used to compute the address of the base of the thread-local storage block for the current module. The descriptor for the module must have been loaded with !tlsldm!N.

!gpdisp!N

Used with ldah and lda to load the GP from the current address, a-la the ldgp macro. The source register for the ldah instruction must contain the address of the ldah instruction. There must be exactly one lda instruction paired with the ldah instruction, though it may appear anywhere in the instruction stream. The immediate operands must be zero.

bsr $26,foo ldah $29,0($26) !gpdisp!1 lda $29,0($29) !gpdisp!1

!gprelhigh

Used with an ldah instruction to add the high 16 bits of a 32-bit displacement from the GP.

!gprellow

Used with any memory format instruction to add the low 16 bits of a 32-bit displacement from the GP.

!gprel

Used with any memory format instruction to add a 16-bit displacement from the GP.

!samegp

Used with any branch format instruction to skip the GP load at the target address. The referenced symbol must have the same GP as the source object file, and it must be declared to either not use $27 or perform a standard GP load in the first two instructions via the .prologue directive.

!tlsgd

!tlsgd!N

Used with an lda instruction to load the address of a TLS descriptor for a symbol in the GOT.

The sequence number N is optional, and if present it used to pair the descriptor load with both the literal loading the address of the __tls_get_addr function and the lituse_tlsgd marking the call to that function.

For proper relaxation, both the tlsgd, literal and lituse relocations must be in the same extended basic block. That is, the relocation with the lowest address must be executed first at runtime.

!tlsldm

!tlsldm!N

Used with an lda instruction to load the address of a TLS descriptor for the current module in the GOT.

Similar in other respects to tlsgd.

!gotdtprel

Used with an ldq instruction to load the offset of the TLS symbol within its module's thread-local storage block. Also known as the dynamic thread pointer offset or dtp-relative offset.

!dtprelhi

!dtprello

!dtprel

Like gprel relocations except they compute dtp-relative offsets.

!gottprel

Used with an ldq instruction to load the offset of the TLS symbol from the thread pointer. Also known as the tp-relative offset.

!tprelhi

!tprello

!tprel

Like gprel relocations except they compute tp-relative offsets.

8.2.4 Floating Point

8.2.5 Alpha Assembler Directives

as for the Alpha supports many additional directives for compatibility with the native assembler. This section describes them only briefly.

These are the additional directives in as for the Alpha:

.arch cpu

Specifies the target processor. This is equivalent to the `-mcpu' command-line option. See section Options, for a list of values for cpu.

.ent function[, n]

Mark the beginning of function. An optional number may follow for compatibility with the OSF/1 assembler, but is ignored. When generating .mdebug information, this will create a procedure descriptor for the function. In ELF, it will mark the symbol as a function a-la the generic .type directive.

.end function

Mark the end of function. In ELF, it will set the size of the symbol a-la the generic .size directive.

.mask mask, offset

Indicate which of the integer registers are saved in the current function's stack frame. mask is interpreted a bit mask in which bit n set indicates that register n is saved. The registers are saved in a block located offset bytes from the canonical frame address (CFA) which is the value of the stack pointer on entry to the function. The registers are saved sequentially, except that the return address register (normally $26) is saved first.

This and the other directives that describe the stack frame are currently only used when generating .mdebug information. They may in the future be used to generate DWARF2 .debug_frame unwind information for hand written assembly.

.fmask mask, offset

Indicate which of the floating-point registers are saved in the current stack frame. The mask and offset parameters are interpreted as with .mask.

.frame framereg, frameoffset, retreg[, argoffset]

Describes the shape of the stack frame. The frame pointer in use is framereg; normally this is either $fp or $sp. The frame pointer is frameoffset bytes below the CFA. The return address is initially located in retreg until it is saved as indicated in .mask. For compatibility with OSF/1 an optional argoffset parameter is accepted and ignored. It is believed to indicate the offset from the CFA to the saved argument registers.

.prologue n

Indicate that the stack frame is set up and all registers have been spilled. The argument n indicates whether and how the function uses the incoming procedure vector (the address of the called function) in $27. 0 indicates that $27 is not used; 1 indicates that the first two instructions of the function use $27 to perform a load of the GP register; 2 indicates that $27 is used in some non-standard way and so the linker cannot elide the load of the procedure vector during relaxation.

.usepv function, which

Used to indicate the use of the $27 register, similar to .prologue, but without the other semantics of needing to be inside an open .ent/.end block.

The which argument should be either no, indicating that $27 is not used, or std, indicating that the first two instructions of the function perform a GP load.

One might use this directive instead of .prologue if you are also using dwarf2 CFI directives.

.gprel32 expression

Computes the difference between the address in expression and the GP for the current object file, and stores it in 4 bytes. In addition to being smaller than a full 8 byte address, this also does not require a dynamic relocation when used in a shared library.

.t_floating expression

Stores expression as an IEEE double precision value.

.s_floating expression

Stores expression as an IEEE single precision value.

.f_floating expression

Stores expression as a VAX F format value.

.g_floating expression

Stores expression as a VAX G format value.

.d_floating expression

Stores expression as a VAX D format value.

.set feature

Enables or disables various assembler features. Using the positive name of the feature enables while using `nofeature' disables.

at

Indicates that macro expansions may clobber the assembler temporary ($at or $28) register. Some macros may not be expanded without this and will generate an error message if noat is in effect. When at is in effect, a warning will be generated if $at is used by the programmer.

macro

Enables the expansion of macro instructions. Note that variants of real instructions, such as br label vs br $31,label are considered alternate forms and not macros.

move

reorder

volatile

These control whether and how the assembler may re-order instructions. Accepted for compatibility with the OSF/1 assembler, but as does not do instruction scheduling, so these features are ignored.

The following directives are recognized for compatibility with the OSF/1 assembler but are ignored.

.proc .aproc .reguse .livereg .option .aent .ugen .eflag .alias .noalias

8.2.6 Opcodes

8.3 ARC Dependent Features

8.3.1 Options
8.3.2 Syntax
8.3.3 Floating Point
8.3.4 ARC Machine Directives
8.3.5 Opcodes

8.3.1 Options

-marc[5|6|7|8]

This option selects the core processor variant. Using -marc is the same as -marc6, which is also the default.

arc5

Base instruction set.

arc6

Jump-and-link (jl) instruction. No requirement of an instruction between setting flags and conditional jump. For example:

mov.f r0,r1 beq foo

arc7

Break (brk) and sleep (sleep) instructions.

arc8

Software interrupt (swi) instruction.

Note: the .option directive can to be used to select a core variant from within assembly code.

-EB

This option specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor.

-EL

This option specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor - this is the default.

8.3.2 Syntax

8.3.2.1 Special Characters
8.3.2.2 Register Names

8.3.2.1 Special Characters

*TODO*

8.3.2.2 Register Names

*TODO*

8.3.3 Floating Point

The ARC core does not currently have hardware floating point support. Software floating point support is provided by GCC and uses IEEE floating-point numbers.

8.3.4 ARC Machine Directives

The ARC version of as supports the following additional machine directives:

.2byte expressions

*TODO*

.3byte expressions

*TODO*

.4byte expressions

*TODO*

.extAuxRegister name,address,mode

*TODO*

.extAuxRegister mulhi,0x12,w

.extCondCode suffix,value

*TODO*

.extCondCode is_busy,0x14

.extCoreRegister name,regnum,mode,shortcut

*TODO*

.extCoreRegister mlo,57,r,can_shortcut

.extInstruction name,opcode,subopcode,suffixclass,syntaxclass

*TODO*

.extInstruction mul64,0x14,0x0,SUFFIX_COND,SYNTAX_3OP|OP1_MUST_BE_IMM

.half expressions

*TODO*

.long expressions

*TODO*

.option arc|arc5|arc6|arc7|arc8

The .option directive must be followed by the desired core version. Again arc is an alias for arc6.

Note: the .option directive overrides the command line option -marc; a warning is emitted when the version is not consistent between the two - even for the implicit default core version (arc6).

.short expressions

*TODO*

.word expressions

*TODO*

8.3.5 Opcodes

For information on the ARC instruction set, see ARC Programmers Reference Manual, ARC Cores Ltd.

8.4 ARM Dependent Features

8.4.1 Options
8.4.2 Syntax
8.4.3 Floating Point
8.4.4 ARM Machine Directives
8.4.5 Opcodes
8.4.6 Mapping Symbols

8.4.1 Options

-mcpu=processor[+extension...]

This option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are recognized: arm1, arm2, arm250, arm3, arm6, arm60, arm600, arm610, arm620, arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, arm700i, arm710, arm710t, arm720, arm720t, arm740t, arm710c, arm7100, arm7500, arm7500fe, arm7t, arm7tdmi, arm8, arm810, strongarm, strongarm1, strongarm110, strongarm1100, strongarm1110, arm9, arm920, arm920t, arm922t, arm940t, arm9tdmi, arm9e, arm926e, arm926ejs, arm946e-r0, arm946e, arm966e-r0, arm966e, arm10t, arm10e, arm1020, arm1020t, arm1020e, arm1026ejs, arm1136js, arm1136jfs, ep9312 (ARM920 with Cirrus Maverick coprocessor), i80200 (Intel XScale processor) iwmmxt (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor) and xscale. The special name all may be used to allow the assembler to accept instructions valid for any ARM processor.

In addition to the basic instruction set, the assembler can be told to accept various extension mnemonics that extend the processor using the co-processor instruction space. For example, -mcpu=arm920+maverick is equivalent to specifying -mcpu=ep9312. The following extensions are currently supported: +maverick +iwmmxt and +xscale.

-march=architecture[+extension...]

This option specifies the target architecture. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target architecture. The following architecture names are recognized: armv1, armv2, armv2a, armv2s, armv3, armv3m, armv4, armv4xm, armv4t, armv4txm, armv5, armv5t, armv5txm, armv5te, armv5texp, armv6, armv6j, iwmmxt and xscale. If both -mcpu and -march are specified, the assembler will use the setting for -mcpu.

The architecture option can be extended with the same instruction set extension options as the -mcpu option.

-mfpu=floating-point-format

This option specifies the floating point format to assemble for. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target floating point unit. The following format options are recognized: softfpa, fpe, fpe2, fpe3, fpa, fpa10, fpa11, arm7500fe, softvfp, softvfp+vfp, vfp, vfp10, vfp10-r0, vfp9, vfpxd, arm1020t, arm1020e, arm1136jfs and maverick.

In addition to determining which instructions are assembled, this option also affects the way in which the .double assembler directive behaves when assembling little-endian code.

The default is dependent on the processor selected. For Architecture 5 or later, the default is to assembler for VFP instructions; for earlier architectures the default is to assemble for FPA instructions.

-mthumb

This option specifies that the assembler should start assembling Thumb instructions; that is, it should behave as though the file starts with a .code 16 directive.

-mthumb-interwork

This option specifies that the output generated by the assembler should be marked as supporting interworking.

-mapcs [26|32]

This option specifies that the output generated by the assembler should be marked as supporting the indicated version of the Arm Procedure. Calling Standard.

-matpcs

This option specifies that the output generated by the assembler should be marked as supporting the Arm/Thumb Procedure Calling Standard. If enabled this option will cause the assembler to create an empty debugging section in the object file called .arm.atpcs. Debuggers can use this to determine the ABI being used by.

-mapcs-float

This indicates the floating point variant of the APCS should be used. In this variant floating point arguments are passed in FP registers rather than integer registers.

-mapcs-reentrant

This indicates that the reentrant variant of the APCS should be used. This variant supports position independent code.

-mfloat-abi=abi

This option specifies that the output generated by the assembler should be marked as using specified floating point ABI. The following values are recognized: soft, softfp and hard.

-EB

This option specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor.

-EL

This option specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor.

-k

This option specifies that the output of the assembler should be marked as position-independent code (PIC).

-moabi

This indicates that the code should be assembled using the old ARM ELF conventions, based on a beta release release of the ARM-ELF specifications, rather than the default conventions which are based on the final release of the ARM-ELF specifications.

8.4.2 Syntax

8.4.2.1 Special Characters
8.4.2.2 Register Names

8.4.2.1 Special Characters

The presence of a `@' on a line indicates the start of a comment that extends to the end of the current line. If a `#' appears as the first character of a line, the whole line is treated as a comment.

The `;' character can be used instead of a newline to separate statements.

Either `#' or `$' can be used to indicate immediate operands.

*TODO* Explain about /data modifier on symbols.

8.4.2.2 Register Names

*TODO* Explain about ARM register naming, and the predefined names.

8.4.3 Floating Point

The ARM family uses IEEE floating-point numbers.

8.4.4 ARM Machine Directives

.align expression [, expression]

This is the generic .align directive. For the ARM however if the first argument is zero (ie no alignment is needed) the assembler will behave as if the argument had been 2 (ie pad to the next four byte boundary). This is for compatibility with ARM's own assembler.

name .req register name

This creates an alias for register name called name. For example:

foo .req r0

.unreq alias-name

This undefines a register alias which was previously defined using the req directive. For example:

foo .req r0 .unreq foo

An error occurs if the name is undefined. Note - this pseudo op can be used to delete builtin in register name aliases (eg 'r0'). This should only be done if it is really necessary.

.code [16|32]

This directive selects the instruction set being generated. The value 16 selects Thumb, with the value 32 selecting ARM.

.thumb

This performs the same action as .code 16.

.arm

This performs the same action as .code 32.

.force_thumb

This directive forces the selection of Thumb instructions, even if the target processor does not support those instructions

.thumb_func

This directive specifies that the following symbol is the name of a Thumb encoded function. This information is necessary in order to allow the assembler and linker to generate correct code for interworking between Arm and Thumb instructions and should be used even if interworking is not going to be performed. The presence of this directive also implies .thumb

.thumb_set

This performs the equivalent of a .set directive in that it creates a symbol which is an alias for another symbol (possibly not yet defined). This directive also has the added property in that it marks the aliased symbol as being a thumb function entry point, in the same way that the .thumb_func directive does.

.ltorg

This directive causes the current contents of the literal pool to be dumped into the current section (which is assumed to be the .text section) at the current location (aligned to a word boundary). GAS maintains a separate literal pool for each section and each sub-section. The .ltorg directive will only affect the literal pool of the current section and sub-section. At the end of assembly all remaining, un-empty literal pools will automatically be dumped.

Note - older versions of GAS would dump the current literal pool any time a section change occurred. This is no longer done, since it prevents accurate control of the placement of literal pools.

.pool

This is a synonym for .ltorg.

8.4.5 Opcodes

as implements all the standard ARM opcodes. It also implements several pseudo opcodes, including several synthetic load instructions.

NOP

nop

This pseudo op will always evaluate to a legal ARM instruction that does nothing. Currently it will evaluate to MOV r0, r0.

LDR

ldr <register> , = <expression>

If expression evaluates to a numeric constant then a MOV or MVN instruction will be used in place of the LDR instruction, if the constant can be generated by either of these instructions. Otherwise the constant will be placed into the nearest literal pool (if it not already there) and a PC relative LDR instruction will be generated.

ADR

adr <register> <label>

This instruction will load the address of label into the indicated register. The instruction will evaluate to a PC relative ADD or SUB instruction depending upon where the label is located. If the label is out of range, or if it is not defined in the same file (and section) as the ADR instruction, then an error will be generated. This instruction will not make use of the literal pool.

ADRL

adrl <register> <label>

This instruction will load the address of label into the indicated register. The instruction will evaluate to one or two PC relative ADD or SUB instructions depending upon where the label is located. If a second instruction is not needed a NOP instruction will be generated in its place, so that this instruction is always 8 bytes long.

If the label is out of range, or if it is not defined in the same file (and section) as the ADRL instruction, then an error will be generated. This instruction will not make use of the literal pool.

For information on the ARM or Thumb instruction sets, see ARM Software Development Toolkit Reference Manual, Advanced RISC Machines Ltd.

8.4.6 Mapping Symbols

The ARM ELF specification requires that special symbols be inserted into object files to mark certain features:

$a

At the start of a region of code containing ARM instructions.

$t

At the start of a region of code containing THUMB instructions.

$d

At the start of a region of data.

The assembler will automatically insert these symbols for you - there is no need to code them yourself. Support for tagging symbols ($b, $f, $p and $m) which is also mentioned in the current ARM ELF specification is not implemented. This is because they have been dropped from the new EABI and so tools cannot rely upon their presence.

8.5 CRIS Dependent Features

8.5.1 Command-line Options
8.5.2 Instruction expansion
8.5.3 Syntax

8.5.1 Command-line Options

The CRIS version of as has these machine-dependent command-line options.

The format of the generated object files can be either ELF or a.out, specified by the command-line options `--emulation=crisaout' and `--emulation=criself'. The default is ELF (criself), unless as has been configured specifically for a.out by using the configuration name cris-axis-aout.

There are two different link-incompatible ELF object file variants for CRIS, for use in environments where symbols are expected to be prefixed by a leading `_' character and for environments without such a symbol prefix. The variant used for GNU/Linux port has no symbol prefix. Which variant to produce is specified by either of the options `--underscore' and `--no-underscore'. The default is `--underscore'. Since symbols in CRIS a.out objects are expected to have a `_' prefix, specifying `--no-underscore' when generating a.out objects is an error. Besides the object format difference, the effect of this option is to parse register names differently (see crisnous). The `--no-underscore' option makes a `$' register prefix mandatory.

The option `--pic' must be passed to as in order to recognize the symbol syntax used for ELF (SVR4 PIC) position-independent-code (see crispic). This will also affect expansion of instructions. The expansion with `--pic' will use PC-relative rather than (slightly faster) absolute addresses in those expansions.

When `-N' is specified, as will emit a warning when a 16-bit branch instruction is expanded into a 32-bit multiple-instruction construct (see section 8.5.2 Instruction expansion).

Some versions of the CRIS v10, for example in the Etrax 100 LX, contain a bug that causes destabilizing memory accesses when a multiply instruction is executed with certain values in the first operand just before a cache-miss. When the `--mul-bug-abort' command line option is active (the default value), as will refuse to assemble a file containing a multiply instruction at a dangerous offset, one that could be the last on a cache-line, or is in a section with insufficient alignment. This placement checking does not catch any case where the multiply instruction is dangerously placed because it is located in a delay-slot. The `--mul-bug-abort' command line option turns off the checking.

8.5.2 Instruction expansion

as will silently choose an instruction that fits the operand size for `[register+constant]' operands. For example, the offset 127 in move.d [r3+127],r4 fits in an instruction using a signed-byte offset. Similarly, move.d [r2+32767],r1 will generate an instruction using a 16-bit offset. For symbolic expressions and constants that do not fit in 16 bits including the sign bit, a 32-bit offset is generated.

For branches, as will expand from a 16-bit branch instruction into a sequence of instructions that can reach a full 32-bit address. Since this does not correspond to a single instruction, such expansions can optionally be warned about. See section 8.5.1 Command-line Options.

8.5.3 Syntax

There are different aspects of the CRIS assembly syntax.

8.5.3.1 Special Characters
8.5.3.2 Symbols in position-independent code		Position-Independent Code Symbols
8.5.3.3 Register names		Register Names
8.5.3.4 Assembler Directives

8.5.3.1 Special Characters

The character `#' is a line comment character. It starts a comment if and only if it is placed at the beginning of a line.

A `;' character starts a comment anywhere on the line, causing all characters up to the end of the line to be ignored.

A `@' character is handled as a line separator equivalent to a logical new-line character (except in a comment), so separate instructions can be specified on a single line.

8.5.3.2 Symbols in position-independent code

When generating position-independent code (SVR4 PIC) for use in cris-axis-linux-gnu shared libraries, symbol suffixes are used to specify what kind of run-time symbol lookup will be used, expressed in the object as different relocation types. Usually, all absolute symbol values must be located in a table, the global offset table, leaving the code position-independent; independent of values of global symbols and independent of the address of the code. The suffix modifies the value of the symbol, into for example an index into the global offset table where the real symbol value is entered, or a PC-relative value, or a value relative to the start of the global offset table. All symbol suffixes start with the character `:' (omitted in the list below). Every symbol use in code or a read-only section must therefore have a PIC suffix to enable a useful shared library to be created. Usually, these constructs must not be used with an additive constant offset as is usually allowed, i.e. no 4 as in symbol + 4 is allowed. This restriction is checked at link-time, not at assembly-time.

GOT

Attaching this suffix to a symbol in an instruction causes the symbol to be entered into the global offset table. The value is a 32-bit index for that symbol into the global offset table. The name of the corresponding relocation is `R_CRIS_32_GOT'. Example: move.d [$r0+extsym:GOT],$r9

GOT16

Same as for `GOT', but the value is a 16-bit index into the global offset table. The corresponding relocation is `R_CRIS_16_GOT'. Example: move.d [$r0+asymbol:GOT16],$r10

PLT

This suffix is used for function symbols. It causes a procedure linkage table, an array of code stubs, to be created at the time the shared object is created or linked against, together with a global offset table entry. The value is a pc-relative offset to the corresponding stub code in the procedure linkage table. This arrangement causes the run-time symbol resolver to be called to look up and set the value of the symbol the first time the function is called (at latest; depending environment variables). It is only safe to leave the symbol unresolved this way if all references are function calls. The name of the relocation is `R_CRIS_32_PLT_PCREL'. Example: add.d fnname:PLT,$pc

PLTG

Like PLT, but the value is relative to the beginning of the global offset table. The relocation is `R_CRIS_32_PLT_GOTREL'. Example: move.d fnname:PLTG,$r3

GOTPLT

Similar to `PLT', but the value of the symbol is a 32-bit index into the global offset table. This is somewhat of a mix between the effect of the `GOT' and the `PLT' suffix; the difference to `GOT' is that there will be a procedure linkage table entry created, and that the symbol is assumed to be a function entry and will be resolved by the run-time resolver as with `PLT'. The relocation is `R_CRIS_32_GOTPLT'. Example: jsr [$r0+fnname:GOTPLT]

GOTPLT16

A variant of `GOTPLT' giving a 16-bit value. Its relocation name is `R_CRIS_16_GOTPLT'. Example: jsr [$r0+fnname:GOTPLT16]

GOTOFF

This suffix must only be attached to a local symbol, but may be used in an expression adding an offset. The value is the address of the symbol relative to the start of the global offset table. The relocation name is `R_CRIS_32_GOTREL'. Example: move.d [$r0+localsym:GOTOFF],r3

8.5.3.3 Register names

A `$' character may always prefix a general or special register name in an instruction operand but is mandatory when the option `--no-underscore' is specified or when the .syntax register_prefix directive is in effect (see crisnous). Register names are case-insensitive.

8.5.3.4 Assembler Directives

There are a few CRIS-specific pseudo-directives in addition to the generic ones. See section 7. Assembler Directives. Constants emitted by pseudo-directives are in little-endian order for CRIS. There is no support for floating-point-specific directives for CRIS.

.dword EXPRESSIONS

The .dword directive is a synonym for .int, expecting zero or more EXPRESSIONS, separated by commas. For each expression, a 32-bit little-endian constant is emitted.

.syntax ARGUMENT

The .syntax directive takes as ARGUMENT one of the following case-sensitive choices.

no_register_prefix

The .syntax no_register_prefix directive makes a `$' character prefix on all registers optional. It overrides a previous setting, including the corresponding effect of the option `--no-underscore'. If this directive is used when ordinary symbols do not have a `_' character prefix, care must be taken to avoid ambiguities whether an operand is a register or a symbol; using symbols with names the same as general or special registers then invoke undefined behavior.

register_prefix

This directive makes a `$' character prefix on all registers mandatory. It overrides a previous setting, including the corresponding effect of the option `--underscore'.

leading_underscore

This is an assertion directive, emitting an error if the `--no-underscore' option is in effect.

no_leading_underscore

This is the opposite of the .syntax leading_underscore directive and emits an error if the option `--underscore' is in effect.

8.6 D10V Dependent Features

8.6.1 D10V Options
8.6.2 Syntax
8.6.3 Floating Point
8.6.4 Opcodes

8.6.1 D10V Options

`-O'

The D10V can often execute two sub-instructions in parallel. When this option is used, as will attempt to optimize its output by detecting when instructions can be executed in parallel.

`--nowarnswap'

To optimize execution performance, as will sometimes swap the order of instructions. Normally this generates a warning. When this option is used, no warning will be generated when instructions are swapped.

`--gstabs-packing'

`--no-gstabs-packing'

as packs adjacent short instructions into a single packed instruction. `--no-gstabs-packing' turns instruction packing off if `--gstabs' is specified as well; `--gstabs-packing' (the default) turns instruction packing on even when `--gstabs' is specified.

8.6.2 Syntax

The D10V syntax is based on the syntax in Mitsubishi's D10V architecture manual. The differences are detailed below.

8.6.2.1 Size Modifiers
8.6.2.2 Sub-Instructions
8.6.2.3 Special Characters
8.6.2.4 Register Names
8.6.2.5 Addressing Modes
8.6.2.6 @WORD Modifier

8.6.2.1 Size Modifiers

8.6.2.2 Sub-Instructions

If you do not want the assembler automatically making these decisions, you can control the packaging and execution type (parallel or sequential) with the special execution symbols described in the next section.

8.6.2.3 Special Characters

`->'

Sequential with instruction on the left first.

`<-'

Sequential with instruction on the right first.

`||'

Parallel

abs a1 -> abs r0

Execute these sequentially. The instruction on the right is in the right container and is executed second.

abs r0 <- abs a1

Execute these reverse-sequentially. The instruction on the right is in the right container, and is executed first.

ld2w r2,@r8+ || mac a0,r0,r7

Execute these in parallel.

ld2w r2,@r8+ ||

mac a0,r0,r7

Two-line format. Execute these in parallel.

ld2w r2,@r8+

mac a0,r0,r7

Two-line format. Execute these sequentially. Assembler will put them in the proper containers.

ld2w r2,@r8+ ->

mac a0,r0,r7

Two-line format. Execute these sequentially. Same as above but second instruction will always go into right container.

8.6.2.4 Register Names

Register Pairs

r0-r1

r2-r3

r4-r5

r6-r7

r8-r9

r10-r11

r12-r13

r14-r15

The D10V also has predefined symbols for these control registers and status bits:

psw

Processor Status Word

bpsw

Backup Processor Status Word

pc

Program Counter

bpc

Backup Program Counter

rpt_c

Repeat Count

rpt_s

Repeat Start address

rpt_e

Repeat End address

mod_s

Modulo Start address

mod_e

Modulo End address

iba

Instruction Break Address

f0

Flag 0

f1

Flag 1

c

Carry flag

8.6.2.5 Addressing Modes

Rn

Register direct

@Rn

Register indirect

@Rn+

Register indirect with post-increment

@Rn-

Register indirect with post-decrement

@-SP

Register indirect with pre-decrement

@(disp, Rn)

Register indirect with displacement

addr

PC relative address (for branch or rep).

#imm

Immediate data (the `#' is optional and ignored)

8.6.2.6 @WORD Modifier

ldi     r2, main@word
jmp     r2

8.6.3 Floating Point

8.6.4 Opcodes

8.7 D30V Dependent Features

8.7.1 D30V Options
8.7.2 Syntax
8.7.3 Floating Point
8.7.4 Opcodes

8.7.1 D30V Options

`-O'

The D30V can often execute two sub-instructions in parallel. When this option is used, as will attempt to optimize its output by detecting when instructions can be executed in parallel.

`-n'

When this option is used, as will issue a warning every time it adds a nop instruction.

`-N'

When this option is used, as will issue a warning if it needs to insert a nop after a 32-bit multiply before a load or 16-bit multiply instruction.

8.7.2 Syntax

The D30V syntax is based on the syntax in Mitsubishi's D30V architecture manual. The differences are detailed below.

8.7.2.1 Size Modifiers
8.7.2.2 Sub-Instructions
8.7.2.3 Special Characters
8.7.2.4 Guarded Execution
8.7.2.5 Register Names
8.7.2.6 Addressing Modes

8.7.2.1 Size Modifiers

8.7.2.2 Sub-Instructions

If you do not want the assembler automatically making these decisions, you can control the packaging and execution type (parallel or sequential) with the special execution symbols described in the next section.

8.7.2.3 Special Characters

To specify the executing order, use the following symbols:

`->'

Sequential with instruction on the left first.

`<-'

Sequential with instruction on the right first.

`||'

Parallel

The D30V syntax allows either one instruction per line, one instruction per line with the execution symbol, or two instructions per line. For example

abs r2,r3 -> abs r4,r5

Execute these sequentially. The instruction on the right is in the right container and is executed second.

abs r2,r3 <- abs r4,r5

Execute these reverse-sequentially. The instruction on the right is in the right container, and is executed first.

abs r2,r3 || abs r4,r5

Execute these in parallel.

ldw r2,@(r3,r4) ||

mulx r6,r8,r9

Two-line format. Execute these in parallel.

mulx a0,r8,r9

stw r2,@(r3,r4)

Two-line format. Execute these sequentially unless `-O' option is used. If the `-O' option is used, the assembler will determine if the instructions could be done in parallel (the above two instructions can be done in parallel), and if so, emit them as parallel instructions. The assembler will put them in the proper containers. In the above example, the assembler will put the `stw' instruction in left container and the `mulx' instruction in the right container.

stw r2,@(r3,r4) ->

mulx a0,r8,r9

Two-line format. Execute the `stw' instruction followed by the `mulx' instruction sequentially. The first instruction goes in the left container and the second instruction goes into right container. The assembler will give an error if the machine ordering constraints are violated.

stw r2,@(r3,r4) <-

mulx a0,r8,r9

Same as previous example, except that the `mulx' instruction is executed before the `stw' instruction.

Since `$' has no special meaning, you may use it in symbol names.

8.7.2.4 Guarded Execution

`/tx'

Execute the instruction if flag f0 is true.

`/fx'

Execute the instruction if flag f0 is false.

`/xt'

Execute the instruction if flag f1 is true.

`/xf'

Execute the instruction if flag f1 is false.

`/tt'

Execute the instruction if both flags f0 and f1 are true.

`/tf'

Execute the instruction if flag f0 is true and flag f1 is false.

8.7.2.5 Register Names

The D30V also has predefined symbols for these control registers and status bits:

psw

Processor Status Word

bpsw

Backup Processor Status Word

pc

Program Counter

bpc

Backup Program Counter

rpt_c

Repeat Count

rpt_s

Repeat Start address

rpt_e

Repeat End address

mod_s

Modulo Start address

mod_e

Modulo End address

iba

Instruction Break Address

f0

Flag 0

f1

Flag 1

f2

Flag 2

f3

Flag 3

f4

Flag 4

f5

Flag 5

f6

Flag 6

f7

Flag 7

s

Same as flag 4 (saturation flag)

v

Same as flag 5 (overflow flag)

va

Same as flag 6 (sticky overflow flag)

c

Same as flag 7 (carry/borrow flag)

b

Same as flag 7 (carry/borrow flag)

8.7.2.6 Addressing Modes

Rn

Register direct

@Rn

Register indirect

@Rn+

Register indirect with post-increment

@Rn-

Register indirect with post-decrement

@-SP

Register indirect with pre-decrement

@(disp, Rn)

Register indirect with displacement

addr

PC relative address (for branch or rep).

#imm

Immediate data (the `#' is optional and ignored)

8.7.3 Floating Point

8.7.4 Opcodes

8.8 H8/300 Dependent Features

8.8.1 Options
8.8.2 Syntax
8.8.3 Floating Point
8.8.4 H8/300 Machine Directives
8.8.5 Opcodes

8.8.1 Options

as has no additional command-line options for the Renesas (formerly Hitachi) H8/300 family.

8.8.2 Syntax

8.8.2.1 Special Characters
8.8.2.2 Register Names
8.8.2.3 Addressing Modes

8.8.2.1 Special Characters

`;' is the line comment character.

`$' can be used instead of a newline to separate statements. Therefore you may not use `$' in symbol names on the H8/300.

8.8.2.2 Register Names

You can use predefined symbols of the form `rnh' and `rnl' to refer to the H8/300 registers as sixteen 8-bit general-purpose registers. n is a digit from `0' to `7'); for instance, both `r0h' and `r7l' are valid register names.

You can also use the eight predefined symbols `rn' to refer to the H8/300 registers as 16-bit registers (you must use this form for addressing).

On the H8/300H, you can also use the eight predefined symbols `ern' (`er0' ... `er7') to refer to the 32-bit general purpose registers.

The two control registers are called pc (program counter; a 16-bit register, except on the H8/300H where it is 24 bits) and ccr (condition code register; an 8-bit register). r7 is used as the stack pointer, and can also be called sp.

8.8.2.3 Addressing Modes

as understands the following addressing modes for the H8/300:

rn

Register direct

@rn

Register indirect

@(d, rn)

@(d:16, rn)

@(d:24, rn)

Register indirect: 16-bit or 24-bit displacement d from register n. (24-bit displacements are only meaningful on the H8/300H.)

@rn+

Register indirect with post-increment

@-rn

Register indirect with pre-decrement

@aa

@aa:8

@aa:16

@aa:24

Absolute address aa. (The address size `:24' only makes sense on the H8/300H.)

#xx

#xx:8

#xx:16

#xx:32

Immediate data xx. You may specify the `:8', `:16', or `:32' for clarity, if you wish; but as neither requires this nor uses it--the data size required is taken from context.

@@aa

@@aa:8

Memory indirect. You may specify the `:8' for clarity, if you wish; but as neither requires this nor uses it.

8.8.3 Floating Point

The H8/300 family has no hardware floating point, but the .float directive generates IEEE floating-point numbers for compatibility with other development tools.

8.8.4 H8/300 Machine Directives

as has the following machine-dependent directives for the H8/300:

.h8300h

Recognize and emit additional instructions for the H8/300H variant, and also make .int emit 32-bit numbers rather than the usual (16-bit) for the H8/300 family.

.h8300s

Recognize and emit additional instructions for the H8S variant, and also make .int emit 32-bit numbers rather than the usual (16-bit) for the H8/300 family.

.h8300hn

Recognize and emit additional instructions for the H8/300H variant in normal mode, and also make .int emit 32-bit numbers rather than the usual (16-bit) for the H8/300 family.

.h8300sn

Recognize and emit additional instructions for the H8S variant in normal mode, and also make .int emit 32-bit numbers rather than the usual (16-bit) for the H8/300 family.

On the H8/300 family (including the H8/300H) `.word' directives generate 16-bit numbers.

8.8.5 Opcodes

For detailed information on the H8/300 machine instruction set, see H8/300 Series Programming Manual. For information specific to the H8/300H, see H8/300H Series Programming Manual (Renesas).

as implements all the standard H8/300 opcodes. No additional pseudo-instructions are needed on this family.

The following table summarizes the H8/300 opcodes, and their arguments. Entries marked `*' are opcodes used only on the H8/300H.

Legend: Rs source register Rd destination register abs absolute address imm immediate data disp:N N-bit displacement from a register pcrel:N N-bit displacement relative to program counter add.b #imm,rd * andc #imm,ccr add.b rs,rd band #imm,rd add.w rs,rd band #imm,@rd * add.w #imm,rd band #imm,@abs:8 * add.l rs,rd bra pcrel:8 * add.l #imm,rd * bra pcrel:16 adds #imm,rd bt pcrel:8 addx #imm,rd * bt pcrel:16 addx rs,rd brn pcrel:8 and.b #imm,rd * brn pcrel:16 and.b rs,rd bf pcrel:8 * and.w rs,rd * bf pcrel:16 * and.w #imm,rd bhi pcrel:8 * and.l #imm,rd * bhi pcrel:16 * and.l rs,rd bls pcrel:8 * bls pcrel:16 bld #imm,rd bcc pcrel:8 bld #imm,@rd * bcc pcrel:16 bld #imm,@abs:8 bhs pcrel:8 bnot #imm,rd * bhs pcrel:16 bnot #imm,@rd bcs pcrel:8 bnot #imm,@abs:8 * bcs pcrel:16 bnot rs,rd blo pcrel:8 bnot rs,@rd * blo pcrel:16 bnot rs,@abs:8 bne pcrel:8 bor #imm,rd * bne pcrel:16 bor #imm,@rd beq pcrel:8 bor #imm,@abs:8 * beq pcrel:16 bset #imm,rd bvc pcrel:8 bset #imm,@rd * bvc pcrel:16 bset #imm,@abs:8 bvs pcrel:8 bset rs,rd * bvs pcrel:16 bset rs,@rd bpl pcrel:8 bset rs,@abs:8 * bpl pcrel:16 bsr pcrel:8 bmi pcrel:8 bsr pcrel:16 * bmi pcrel:16 bst #imm,rd bge pcrel:8 bst #imm,@rd * bge pcrel:16 bst #imm,@abs:8 blt pcrel:8 btst #imm,rd * blt pcrel:16 btst #imm,@rd bgt pcrel:8 btst #imm,@abs:8 * bgt pcrel:16 btst rs,rd ble pcrel:8 btst rs,@rd * ble pcrel:16 btst rs,@abs:8 bclr #imm,rd bxor #imm,rd bclr #imm,@rd bxor #imm,@rd bclr #imm,@abs:8 bxor #imm,@abs:8 bclr rs,rd cmp.b #imm,rd bclr rs,@rd cmp.b rs,rd bclr rs,@abs:8 cmp.w rs,rd biand #imm,rd cmp.w rs,rd biand #imm,@rd * cmp.w #imm,rd biand #imm,@abs:8 * cmp.l #imm,rd bild #imm,rd * cmp.l rs,rd bild #imm,@rd daa rs bild #imm,@abs:8 das rs bior #imm,rd dec.b rs bior #imm,@rd * dec.w #imm,rd bior #imm,@abs:8 * dec.l #imm,rd bist #imm,rd divxu.b rs,rd bist #imm,@rd * divxu.w rs,rd bist #imm,@abs:8 * divxs.b rs,rd bixor #imm,rd * divxs.w rs,rd bixor #imm,@rd eepmov bixor #imm,@abs:8 * eepmovw * exts.w rd mov.w rs,@abs:16 * exts.l rd * mov.l #imm,rd * extu.w rd * mov.l rs,rd * extu.l rd * mov.l @rs,rd inc rs * mov.l @(disp:16,rs),rd * inc.w #imm,rd * mov.l @(disp:24,rs),rd * inc.l #imm,rd * mov.l @rs+,rd jmp @rs * mov.l @abs:16,rd jmp abs * mov.l @abs:24,rd jmp @@abs:8 * mov.l rs,@rd jsr @rs * mov.l rs,@(disp:16,rd) jsr abs * mov.l rs,@(disp:24,rd) jsr @@abs:8 * mov.l rs,@-rd ldc #imm,ccr * mov.l rs,@abs:16 ldc rs,ccr * mov.l rs,@abs:24 * ldc @abs:16,ccr movfpe @abs:16,rd * ldc @abs:24,ccr movtpe rs,@abs:16 * ldc @(disp:16,rs),ccr mulxu.b rs,rd * ldc @(disp:24,rs),ccr * mulxu.w rs,rd * ldc @rs+,ccr * mulxs.b rs,rd * ldc @rs,ccr * mulxs.w rs,rd * mov.b @(disp:24,rs),rd neg.b rs * mov.b rs,@(disp:24,rd) * neg.w rs mov.b @abs:16,rd * neg.l rs mov.b rs,rd nop mov.b @abs:8,rd not.b rs mov.b rs,@abs:8 * not.w rs mov.b rs,rd * not.l rs mov.b #imm,rd or.b #imm,rd mov.b @rs,rd or.b rs,rd mov.b @(disp:16,rs),rd * or.w #imm,rd mov.b @rs+,rd * or.w rs,rd mov.b @abs:8,rd * or.l #imm,rd mov.b rs,@rd * or.l rs,rd mov.b rs,@(disp:16,rd) orc #imm,ccr mov.b rs,@-rd pop.w rs mov.b rs,@abs:8 * pop.l rs mov.w rs,@rd push.w rs * mov.w @(disp:24,rs),rd * push.l rs * mov.w rs,@(disp:24,rd) rotl.b rs * mov.w @abs:24,rd * rotl.w rs * mov.w rs,@abs:24 * rotl.l rs mov.w rs,rd rotr.b rs mov.w #imm,rd * rotr.w rs mov.w @rs,rd * rotr.l rs mov.w @(disp:16,rs),rd rotxl.b rs mov.w @rs+,rd * rotxl.w rs mov.w @abs:16,rd * rotxl.l rs mov.w rs,@(disp:16,rd) rotxr.b rs mov.w rs,@-rd * rotxr.w rs * rotxr.l rs * stc ccr,@(disp:24,rd) bpt * stc ccr,@-rd rte * stc ccr,@abs:16 rts * stc ccr,@abs:24 shal.b rs sub.b rs,rd * shal.w rs sub.w rs,rd * shal.l rs * sub.w #imm,rd shar.b rs * sub.l rs,rd * shar.w rs * sub.l #imm,rd * shar.l rs subs #imm,rd shll.b rs subx #imm,rd * shll.w rs subx rs,rd * shll.l rs * trapa #imm shlr.b rs xor #imm,rd * shlr.w rs xor rs,rd * shlr.l rs * xor.w #imm,rd sleep * xor.w rs,rd stc ccr,rd * xor.l #imm,rd * stc ccr,@rs * xor.l rs,rd * stc ccr,@(disp:16,rd) xorc #imm,ccr

Four H8/300 instructions (add, cmp, mov, sub) are defined with variants using the suffixes `.b', `.w', and `.l' to specify the size of a memory operand. as supports these suffixes, but does not require them; since one of the operands is always a register, as can deduce the correct size.

For example, since r0 refers to a 16-bit register,

mov r0,@foo is equivalent to mov.w r0,@foo

If you use the size suffixes, as issues a warning when the suffix and the register size do not match.

8.9 H8/500 Dependent Features

8.9.1 Options
8.9.2 Syntax
8.9.3 Floating Point
8.9.4 H8/500 Machine Directives
8.9.5 Opcodes

8.9.1 Options

as has no additional command-line options for the Renesas (formerly Hitachi) H8/500 family.

8.9.2 Syntax

8.9.2.1 Special Characters
8.9.2.2 Register Names
8.9.2.3 Addressing Modes

8.9.2.1 Special Characters

`!' is the line comment character.

`;' can be used instead of a newline to separate statements.

Since `$' has no special meaning, you may use it in symbol names.

8.9.2.2 Register Names

You can use the predefined symbols `r0', `r1', `r2', `r3', `r4', `r5', `r6', and `r7' to refer to the H8/500 registers.

The H8/500 also has these control registers:

cp

code pointer

dp

data pointer

bp

base pointer

tp

stack top pointer

ep

extra pointer

sr

status register

ccr

condition code register

All registers are 16 bits long. To represent 32 bit numbers, use two adjacent registers; for distant memory addresses, use one of the segment pointers (cp for the program counter; dp for r0--r3; ep for r4 and r5; and tp for r6 and r7.

8.9.2.3 Addressing Modes

as understands the following addressing modes for the H8/500:

Rn

Register direct

@Rn

Register indirect

@(d:8, Rn)

Register indirect with 8 bit signed displacement

@(d:16, Rn)

Register indirect with 16 bit signed displacement

@-Rn

Register indirect with pre-decrement

@Rn+

Register indirect with post-increment

@aa:8

8 bit absolute address

@aa:16

16 bit absolute address

#xx:8

8 bit immediate

#xx:16

16 bit immediate

8.9.3 Floating Point

The H8/500 family has no hardware floating point, but the .float directive generates IEEE floating-point numbers for compatibility with other development tools.

8.9.4 H8/500 Machine Directives

as has no machine-dependent directives for the H8/500. However, on this platform the `.int' and `.word' directives generate 16-bit numbers.

8.9.5 Opcodes

For detailed information on the H8/500 machine instruction set, see H8/500 Series Programming Manual (Renesas M21T001).

as implements all the standard H8/500 opcodes. No additional pseudo-instructions are needed on this family.

The following table summarizes H8/500 opcodes and their operands:

Legend: abs8 8-bit absolute address abs16 16-bit absolute address abs24 24-bit absolute address crb ccr, br, ep, dp, tp, dp disp8 8-bit displacement ea rn, @rn, @(d:8, rn), @(d:16, rn), @-rn, @rn+, @aa:8, @aa:16, #xx:8, #xx:16 ea_mem @rn, @(d:8, rn), @(d:16, rn), @-rn, @rn+, @aa:8, @aa:16 ea_noimm rn, @rn, @(d:8, rn), @(d:16, rn), @-rn, @rn+, @aa:8, @aa:16 fp r6 imm4 4-bit immediate data imm8 8-bit immediate data imm16 16-bit immediate data pcrel8 8-bit offset from program counter pcrel16 16-bit offset from program counter qim -2, -1, 1, 2 rd any register rs a register distinct from rd rlist comma-separated list of registers in parentheses; register ranges rd-rs are allowed sp stack pointer (r7) sr status register sz size; `.b' or `.w'. If omitted, default `.w' ldc[.b] ea,crb bcc[.w] pcrel16 ldc[.w] ea,sr bcc[.b] pcrel8 add[:q] sz qim,ea_noimm bhs[.w] pcrel16 add[:g] sz ea,rd bhs[.b] pcrel8 adds sz ea,rd bcs[.w] pcrel16 addx sz ea,rd bcs[.b] pcrel8 and sz ea,rd blo[.w] pcrel16 andc[.b] imm8,crb blo[.b] pcrel8 andc[.w] imm16,sr bne[.w] pcrel16 bpt bne[.b] pcrel8 bra[.w] pcrel16 beq[.w] pcrel16 bra[.b] pcrel8 beq[.b] pcrel8 bt[.w] pcrel16 bvc[.w] pcrel16 bt[.b] pcrel8 bvc[.b] pcrel8 brn[.w] pcrel16 bvs[.w] pcrel16 brn[.b] pcrel8 bvs[.b] pcrel8 bf[.w] pcrel16 bpl[.w] pcrel16 bf[.b] pcrel8 bpl[.b] pcrel8 bhi[.w] pcrel16 bmi[.w] pcrel16 bhi[.b] pcrel8 bmi[.b] pcrel8 bls[.w] pcrel16 bge[.w] pcrel16 bls[.b] pcrel8 bge[.b] pcrel8 blt[.w] pcrel16 mov[:g][.b] imm8,ea_mem blt[.b] pcrel8 mov[:g][.w] imm16,ea_mem bgt[.w] pcrel16 movfpe[.b] ea,rd bgt[.b] pcrel8 movtpe[.b] rs,ea_noimm ble[.w] pcrel16 mulxu sz ea,rd ble[.b] pcrel8 neg sz ea bclr sz imm4,ea_noimm nop bclr sz rs,ea_noimm not sz ea bnot sz imm4,ea_noimm or sz ea,rd bnot sz rs,ea_noimm orc[.b] imm8,crb bset sz imm4,ea_noimm orc[.w] imm16,sr bset sz rs,ea_noimm pjmp abs24 bsr[.b] pcrel8 pjmp @rd bsr[.w] pcrel16 pjsr abs24 btst sz imm4,ea_noimm pjsr @rd btst sz rs,ea_noimm prtd imm8 clr sz ea prtd imm16 cmp[:e][.b] imm8,rd prts cmp[:i][.w] imm16,rd rotl sz ea cmp[:g].b imm8,ea_noimm rotr sz ea cmp[:g][.w] imm16,ea_noimm rotxl sz ea Cmp[:g] sz ea,rd rotxr sz ea dadd rs,rd rtd imm8 divxu sz ea,rd rtd imm16 dsub rs,rd rts exts[.b] rd scb/f rs,pcrel8 extu[.b] rd scb/ne rs,pcrel8 jmp @rd scb/eq rs,pcrel8 jmp @(imm8,rd) shal sz ea jmp @(imm16,rd) shar sz ea jmp abs16 shll sz ea jsr @rd shlr sz ea jsr @(imm8,rd) sleep jsr @(imm16,rd) stc[.b] crb,ea_noimm jsr abs16 stc[.w] sr,ea_noimm ldm @sp+,(rlist) stm (rlist),@-sp link fp,imm8 sub sz ea,rd link fp,imm16 subs sz ea,rd mov[:e][.b] imm8,rd subx sz ea,rd mov[:i][.w] imm16,rd swap[.b] rd mov[:l][.w] abs8,rd tas[.b] ea mov[:l].b abs8,rd trapa imm4 mov[:s][.w] rs,abs8 trap/vs mov[:s].b rs,abs8 tst sz ea mov[:f][.w] @(disp8,fp),rd unlk fp mov[:f][.w] rs,@(disp8,fp) xch[.w] rs,rd mov[:f].b @(disp8,fp),rd xor sz ea,rd mov[:f].b rs,@(disp8,fp) xorc.b imm8,crb mov[:g] sz rs,ea_mem xorc.w imm16,sr mov[:g] sz ea,rd

8.10 HPPA Dependent Features

8.10.1 Notes
8.10.2 Options
8.10.3 Syntax
8.10.4 Floating Point
8.10.5 HPPA Assembler Directives		HPPA Machine Directives
8.10.6 Opcodes

8.10.1 Notes

The format of the debugging sections has changed since the original as port (version 1.3X) was released; therefore, you must rebuild all HPPA objects and libraries with the new assembler so that you can debug the final executable.

The HPPA as port generates a small subset of the relocations available in the SOM and ELF object file formats. Additional relocation support will be added as it becomes necessary.

8.10.2 Options

8.10.3 Syntax

First, a colon may immediately follow a label definition. This is simply for compatibility with how most assembly language programmers write code.

Some obscure expression parsing problems may affect hand written code which uses the spop instructions, or code which makes significant use of the ! line separator.

as is much less forgiving about missing arguments and other similar oversights than the HP assembler. as notifies you of missing arguments as syntax errors; this is regarded as a feature, not a bug.

Finally, as allows you to use an external symbol without explicitly importing the symbol. Warning: in the future this will be an error for HPPA targets.

Special characters for HPPA targets include:

`;' is the line comment character.

`!' can be used instead of a newline to separate statements.

Since `$' has no special meaning, you may use it in symbol names.

8.10.4 Floating Point

8.10.5 HPPA Assembler Directives

as for the HPPA supports many additional directives for compatibility with the native assembler. This section describes them only briefly. For detailed information on HPPA-specific assembler directives, see HP9000 Series 800 Assembly Language Reference Manual (HP 92432-90001).

as does not support the following assembler directives described in the HP manual:

.endm .liston .enter .locct .leave .macro .listoff

Beyond those implemented for compatibility, as supports one additional assembler directive for the HPPA: .param. It conveys register argument locations for static functions. Its syntax closely follows the .export directive.

These are the additional directives in as for the HPPA:

.block n

.blockz n

Reserve n bytes of storage, and initialize them to zero.

.call

Mark the beginning of a procedure call. Only the special case with no arguments is allowed.

.callinfo [ param=value, ... ] [ flag, ... ]

Specify a number of parameters and flags that define the environment for a procedure.

param may be any of `frame' (frame size), `entry_gr' (end of general register range), `entry_fr' (end of float register range), `entry_sr' (end of space register range).

The values for flag are `calls' or `caller' (proc has subroutines), `no_calls' (proc does not call subroutines), `save_rp' (preserve return pointer), `save_sp' (proc preserves stack pointer), `no_unwind' (do not unwind this proc), `hpux_int' (proc is interrupt routine).

.code

Assemble into the standard section called `$TEXT$', subsection `$CODE$'.

.copyright "string"

In the SOM object format, insert string into the object code, marked as a copyright string.

.copyright "string"

In the ELF object format, insert string into the object code, marked as a version string.

.enter

Not yet supported; the assembler rejects programs containing this directive.

.entry

Mark the beginning of a procedure.

.exit

Mark the end of a procedure.

.export name [ ,typ ] [ ,param=r ]

Make a procedure name available to callers. typ, if present, must be one of `absolute', `code' (ELF only, not SOM), `data', `entry', `data', `entry', `millicode', `plabel', `pri_prog', or `sec_prog'.

param, if present, provides either relocation information for the procedure arguments and result, or a privilege level. param may be `argwn' (where n ranges from 0 to 3, and indicates one of four one-word arguments); `rtnval' (the procedure's result); or `priv_lev' (privilege level). For arguments or the result, r specifies how to relocate, and must be one of `no' (not relocatable), `gr' (argument is in general register), `fr' (in floating point register), or `fu' (upper half of float register). For `priv_lev', r is an integer.

.half n

Define a two-byte integer constant n; synonym for the portable as directive .short.

.import name [ ,typ ]

Converse of .export; make a procedure available to call. The arguments use the same conventions as the first two arguments for .export.

.label name

Define name as a label for the current assembly location.

.leave

Not yet supported; the assembler rejects programs containing this directive.

.origin lc

Advance location counter to lc. Synonym for the as portable directive .org.

.param name [ ,typ ] [ ,param=r ]

Similar to .export, but used for static procedures.

.proc

Use preceding the first statement of a procedure.

.procend

Use following the last statement of a procedure.

label .reg expr

Synonym for .equ; define label with the absolute expression expr as its value.

.space secname [ ,params ]

Switch to section secname, creating a new section by that name if necessary. You may only use params when creating a new section, not when switching to an existing one. secname may identify a section by number rather than by name.

If specified, the list params declares attributes of the section, identified by keywords. The keywords recognized are `spnum=exp' (identify this section by the number exp, an absolute expression), `sort=exp' (order sections according to this sort key when linking; exp is an absolute expression), `unloadable' (section contains no loadable data), `notdefined' (this section defined elsewhere), and `private' (data in this section not available to other programs).

.spnum secnam

Allocate four bytes of storage, and initialize them with the section number of the section named secnam. (You can define the section number with the HPPA .space directive.)

.string "str"

Copy the characters in the string str to the object file. See section Strings, for information on escape sequences you can use in as strings.

Warning! The HPPA version of .string differs from the usual as definition: it does not write a zero byte after copying str.

.stringz "str"

Like .string, but appends a zero byte after copying str to object file.

.subspa name [ ,params ]

.nsubspa name [ ,params ]

Similar to .space, but selects a subsection name within the current section. You may only specify params when you create a subsection (in the first instance of .subspa for this name).

If specified, the list params declares attributes of the subsection, identified by keywords. The keywords recognized are `quad=expr' ("quadrant" for this subsection), `align=expr' (alignment for beginning of this subsection; a power of two), `access=expr' (value for "access rights" field), `sort=expr' (sorting order for this subspace in link), `code_only' (subsection contains only code), `unloadable' (subsection cannot be loaded into memory), `common' (subsection is common block), `dup_comm' (initialized data may have duplicate names), or `zero' (subsection is all zeros, do not write in object file).

.nsubspa always creates a new subspace with the given name, even if one with the same name already exists.

.version "str"

Write str as version identifier in object code.

8.10.6 Opcodes

8.11 ESA/390 Dependent Features

8.11.1 Notes
8.11.2 Options
8.11.3 Syntax
8.11.4 Floating Point
8.11.5 ESA/390 Assembler Directives		ESA/390 Machine Directives
8.11.6 Opcodes

8.11.1 Notes

When used with the GNU CC compiler, the ESA/390 as will produce correct, fully relocated, functional binaries, and has been used to compile and execute large projects. However, many aspects should still be considered experimental; these include shared library support, dynamically loadable objects, and any relocation other than the 31-bit relocation.

8.11.2 Options

8.11.3 Syntax

A leading dot in front of directives is optional, and the case of directives is ignored; thus for example, .using and USING have the same effect.

A colon may immediately follow a label definition. This is simply for compatibility with how most assembly language programmers write code.

`#' is the line comment character.

`;' can be used instead of a newline to separate statements.

Since `$' has no special meaning, you may use it in symbol names.

Registers can be given the symbolic names r0..r15, fp0, fp2, fp4, fp6. By using thesse symbolic names, as can detect simple syntax errors. The name rarg or r.arg is a synonym for r11, rtca or r.tca for r12, sp, r.sp, dsa r.dsa for r13, lr or r.lr for r14, rbase or r.base for r3 and rpgt or r.pgt for r4.

`*' is the current location counter. Unlike `.' it is always relative to the last USING directive. Note that this means that expressions cannot use multiplication, as any occurrence of `*' will be interpreted as a location counter.

All labels are relative to the last USING. Thus, branches to a label always imply the use of base+displacement.

Many of the usual forms of address constants / address literals are supported. Thus,

.using *,r3 L r15,=A(some_routine) LM r6,r7,=V(some_longlong_extern) A r1,=F'12' AH r0,=H'42' ME r6,=E'3.1416' MD r6,=D'3.14159265358979' O r6,=XL4'cacad0d0' .ltorg

should all behave as expected: that is, an entry in the literal pool will be created (or reused if it already exists), and the instruction operands will be the displacement into the literal pool using the current base register (as last declared with the .using directive).

8.11.4 Floating Point

8.11.5 ESA/390 Assembler Directives

as for the ESA/390 supports all of the standard ELF/SVR4 assembler directives that are documented in the main part of this documentation. Several additional directives are supported in order to implement the ESA/390 addressing model. The most important of these are .using and .ltorg

These are the additional directives in as for the ESA/390:

.dc

A small subset of the usual DC directive is supported.

.drop regno

Stop using regno as the base register. The regno must have been previously declared with a .using directive in the same section as the current section.

.ebcdic string

Emit the EBCDIC equivalent of the indicated string. The emitted string will be null terminated. Note that the directives .string etc. emit ascii strings by default.

EQU

The standard HLASM-style EQU directive is not supported; however, the standard as directive .equ can be used to the same effect.

.ltorg

Dump the literal pool accumulated so far; begin a new literal pool. The literal pool will be written in the current section; in order to generate correct assembly, a .using must have been previously specified in the same section.

.using expr,regno

Use regno as the base register for all subsequent RX, RS, and SS form instructions. The expr will be evaluated to obtain the base address; usually, expr will merely be `*'.

This assembler allows two .using directives to be simultaneously outstanding, one in the .text section, and one in another section (typically, the .data section). This feature allows dynamically loaded objects to be implemented in a relatively straightforward way. A .using directive must always be specified in the .text section; this will specify the base register that will be used for branches in the .text section. A second .using may be specified in another section; this will specify the base register that is used for non-label address literals. When a second .using is specified, then the subsequent .ltorg must be put in the same section; otherwise an error will result.

Thus, for example, the following code uses r3 to address branch targets and r4 to address the literal pool, which has been written to the .data section. The is, the constants =A(some_routine), =H'42' and =E'3.1416' will all appear in the .data section.

.data .using LITPOOL,r4 .text BASR r3,0 .using *,r3 B START .long LITPOOL START: L r4,4(,r3) L r15,=A(some_routine) LTR r15,r15 BNE LABEL AH r0,=H'42' LABEL: ME r6,=E'3.1416' .data LITPOOL: .ltorg

Note that this dual-.using directive semantics extends and is not compatible with HLASM semantics. Note that this assembler directive does not support the full range of HLASM semantics.

8.11.6 Opcodes

8.12 80386 Dependent Features

The i386 version as supports both the original Intel 386 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture extending the Intel architecture to 64-bits.

8.12.1 Options
8.12.2 AT&T Syntax versus Intel Syntax
8.12.3 Instruction Naming
8.12.4 Register Naming
8.12.5 Instruction Prefixes
8.12.6 Memory References
8.12.7 Handling of Jump Instructions
8.12.8 Floating Point
8.12.9 Intel's MMX and AMD's 3DNow! SIMD Operations
8.12.10 Writing 16-bit Code
8.12.12 Specifying CPU Architecture		Specifying an x86 CPU architecture
8.12.11 AT&T Syntax bugs
8.12.13 Notes

8.12.1 Options

The i386 version of as has a few machine dependent options:

--32 | --64

Select the word size, either 32 bits or 64 bits. Selecting 32-bit implies Intel i386 architecture, while 64-bit implies AMD x86-64 architecture.

These options are only available with the ELF object file format, and require that the necessary BFD support has been included (on a 32-bit platform you have to add --enable-64-bit-bfd to configure enable 64-bit usage and use x86-64 as target platform).

-n

By default, x86 GAS replaces multiple nop instructions used for alignment within code sections with multi-byte nop instructions such as leal 0(%esi,1),%esi. This switch disables the optimization.

8.12.2 AT&T Syntax versus Intel Syntax

as now supports assembly using Intel assembler syntax. .intel_syntax selects Intel mode, and .att_syntax switches back to the usual AT&T mode for compatibility with the output of gcc. Either of these directives may have an optional argument, prefix, or noprefix specifying whether registers require a `%' prefix. AT&T System V/386 assembler syntax is quite different from Intel syntax. We mention these differences because almost all 80386 documents use Intel syntax. Notable differences between the two syntaxes are:

• AT&T immediate operands are preceded by `$'; Intel immediate operands are undelimited (Intel `push 4' is AT&T `pushl $4'). AT&T register operands are preceded by `%'; Intel register operands are undelimited. AT&T absolute (as opposed to PC relative) jump/call operands are prefixed by `*'; they are undelimited in Intel syntax.

• AT&T and Intel syntax use the opposite order for source and destination operands. Intel `add eax, 4' is `addl $4, %eax'. The `source, dest' convention is maintained for compatibility with previous Unix assemblers. Note that instructions with more than one source operand, such as the `enter' instruction, do not have reversed order. 8.12.11 AT&T Syntax bugs.

• In AT&T syntax the size of memory operands is determined from the last character of the instruction mnemonic. Mnemonic suffixes of `b', `w', `l' and `q' specify byte (8-bit), word (16-bit), long (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes this by prefixing memory operands (not the instruction mnemonics) with `byte ptr', `word ptr', `dword ptr' and `qword ptr'. Thus, Intel `mov al, byte ptr foo' is `movb foo, %al' in AT&T syntax.

• Immediate form long jumps and calls are `lcall/ljmp $section, $offset' in AT&T syntax; the Intel syntax is `call/jmp far section:offset'. Also, the far return instruction is `lret $stack-adjust' in AT&T syntax; Intel syntax is `ret far stack-adjust'.

• The AT&T assembler does not provide support for multiple section programs. Unix style systems expect all programs to be single sections.

8.12.3 Instruction Naming

Instruction mnemonics are suffixed with one character modifiers which specify the size of operands. The letters `b', `w', `l' and `q' specify byte, word, long and quadruple word operands. If no suffix is specified by an instruction then as tries to fill in the missing suffix based on the destination register operand (the last one by convention). Thus, `mov %ax, %bx' is equivalent to `movw %ax, %bx'; also, `mov $1, %bx' is equivalent to `movw $1, bx'. Note that this is incompatible with the AT&T Unix assembler which assumes that a missing mnemonic suffix implies long operand size. (This incompatibility does not affect compiler output since compilers always explicitly specify the mnemonic suffix.)

Almost all instructions have the same names in AT&T and Intel format. There are a few exceptions. The sign extend and zero extend instructions need two sizes to specify them. They need a size to sign/zero extend from and a size to zero extend to. This is accomplished by using two instruction mnemonic suffixes in AT&T syntax. Base names for sign extend and zero extend are `movs...' and `movz...' in AT&T syntax (`movsx' and `movzx' in Intel syntax). The instruction mnemonic suffixes are tacked on to this base name, the from suffix before the to suffix. Thus, `movsbl %al, %edx' is AT&T syntax for "move sign extend from %al to %edx." Possible suffixes, thus, are `bl' (from byte to long), `bw' (from byte to word), `wl' (from word to long), `bq' (from byte to quadruple word), `wq' (from word to quadruple word), and `lq' (from long to quadruple word).

The Intel-syntax conversion instructions

• `cbw' -- sign-extend byte in `%al' to word in `%ax',

• `cwde' -- sign-extend word in `%ax' to long in `%eax',

• `cwd' -- sign-extend word in `%ax' to long in `%dx:%ax',

• `cdq' -- sign-extend dword in `%eax' to quad in `%edx:%eax',

• `cdqe' -- sign-extend dword in `%eax' to quad in `%rax' (x86-64 only),

• `cdo' -- sign-extend quad in `%rax' to octuple in `%rdx:%rax' (x86-64 only),

are called `cbtw', `cwtl', `cwtd', `cltd', `cltq', and `cqto' in AT&T naming. as accepts either naming for these instructions.

Far call/jump instructions are `lcall' and `ljmp' in AT&T syntax, but are `call far' and `jump far' in Intel convention.

8.12.4 Register Naming

Register operands are always prefixed with `%'. The 80386 registers consist of

• the 8 32-bit registers `%eax' (the accumulator), `%ebx', `%ecx', `%edx', `%edi', `%esi', `%ebp' (the frame pointer), and `%esp' (the stack pointer).

• the 8 16-bit low-ends of these: `%ax', `%bx', `%cx', `%dx', `%di', `%si', `%bp', and `%sp'.

• the 8 8-bit registers: `%ah', `%al', `%bh', `%bl', `%ch', `%cl', `%dh', and `%dl' (These are the high-bytes and low-bytes of `%ax', `%bx', `%cx', and `%dx')

• the 6 section registers `%cs' (code section), `%ds' (data section), `%ss' (stack section), `%es', `%fs', and `%gs'.

• the 3 processor control registers `%cr0', `%cr2', and `%cr3'.

• the 6 debug registers `%db0', `%db1', `%db2', `%db3', `%db6', and `%db7'.

• the 2 test registers `%tr6' and `%tr7'.

• the 8 floating point register stack `%st' or equivalently `%st(0)', `%st(1)', `%st(2)', `%st(3)', `%st(4)', `%st(5)', `%st(6)', and `%st(7)'. These registers are overloaded by 8 MMX registers `%mm0', `%mm1', `%mm2', `%mm3', `%mm4', `%mm5', `%mm6' and `%mm7'.

• the 8 SSE registers registers `%xmm0', `%xmm1', `%xmm2', `%xmm3', `%xmm4', `%xmm5', `%xmm6' and `%xmm7'.

The AMD x86-64 architecture extends the register set by:

• enhancing the 8 32-bit registers to 64-bit: `%rax' (the accumulator), `%rbx', `%rcx', `%rdx', `%rdi', `%rsi', `%rbp' (the frame pointer), `%rsp' (the stack pointer)

• the 8 extended registers `%r8'--`%r15'.

• the 8 32-bit low ends of the extended registers: `%r8d'--`%r15d'

• the 8 16-bit low ends of the extended registers: `%r8w'--`%r15w'

• the 8 8-bit low ends of the extended registers: `%r8b'--`%r15b'

• the 4 8-bit registers: `%sil', `%dil', `%bpl', `%spl'.

• the 8 debug registers: `%db8'--`%db15'.

• the 8 SSE registers: `%xmm8'--`%xmm15'.

8.12.5 Instruction Prefixes

Instruction prefixes are used to modify the following instruction. They are used to repeat string instructions, to provide section overrides, to perform bus lock operations, and to change operand and address sizes. (Most instructions that normally operate on 32-bit operands will use 16-bit operands if the instruction has an "operand size" prefix.) Instruction prefixes are best written on the same line as the instruction they act upon. For example, the `scas' (scan string) instruction is repeated with:

repne scas %es:(%edi),%al

You may also place prefixes on the lines immediately preceding the instruction, but this circumvents checks that as does with prefixes, and will not work with all prefixes.

Here is a list of instruction prefixes:

• Section override prefixes `cs', `ds', `ss', `es', `fs', `gs'. These are automatically added by specifying using the section:memory-operand form for memory references.

• Operand/Address size prefixes `data16' and `addr16' change 32-bit operands/addresses into 16-bit operands/addresses, while `data32' and `addr32' change 16-bit ones (in a .code16 section) into 32-bit operands/addresses. These prefixes must appear on the same line of code as the instruction they modify. For example, in a 16-bit .code16 section, you might write:

  addr32 jmpl *(%ebx)

• The bus lock prefix `lock' inhibits interrupts during execution of the instruction it precedes. (This is only valid with certain instructions; see a 80386 manual for details).

• The wait for coprocessor prefix `wait' waits for the coprocessor to complete the current instruction. This should never be needed for the 80386/80387 combination.

• The `rep', `repe', and `repne' prefixes are added to string instructions to make them repeat `%ecx' times (`%cx' times if the current address size is 16-bits).
• The `rex' family of prefixes is used by x86-64 to encode extensions to i386 instruction set. The `rex' prefix has four bits -- an operand size overwrite (64) used to change operand size from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the register set.

  You may write the `rex' prefixes directly. The `rex64xyz' instruction emits `rex' prefix with all the bits set. By omitting the 64, x, y or z you may write other prefixes as well. Normally, there is no need to write the prefixes explicitly, since gas will automatically generate them based on the instruction operands.

8.12.6 Memory References

An Intel syntax indirect memory reference of the form

section:[base + index*scale + disp]

is translated into the AT&T syntax

section:disp(base, index, scale)

where base and index are the optional 32-bit base and index registers, disp is the optional displacement, and scale, taking the values 1, 2, 4, and 8, multiplies index to calculate the address of the operand. If no scale is specified, scale is taken to be 1. section specifies the optional section register for the memory operand, and may override the default section register (see a 80386 manual for section register defaults). Note that section overrides in AT&T syntax must be preceded by a `%'. If you specify a section override which coincides with the default section register, as does not output any section register override prefixes to assemble the given instruction. Thus, section overrides can be specified to emphasize which section register is used for a given memory operand.

Here are some examples of Intel and AT&T style memory references:

AT&T: `-4(%ebp)', Intel: `[ebp - 4]'

base is `%ebp'; disp is `-4'. section is missing, and the default section is used (`%ss' for addressing with `%ebp' as the base register). index, scale are both missing.

AT&T: `foo(,%eax,4)', Intel: `[foo + eax*4]'

index is `%eax' (scaled by a scale 4); disp is `foo'. All other fields are missing. The section register here defaults to `%ds'.

AT&T: `foo(,1)'; Intel `[foo]'

This uses the value pointed to by `foo' as a memory operand. Note that base and index are both missing, but there is only one `,'. This is a syntactic exception.

AT&T: `%gs:foo'; Intel `gs:foo'

This selects the contents of the variable `foo' with section register section being `%gs'.

Absolute (as opposed to PC relative) call and jump operands must be prefixed with `*'. If no `*' is specified, as always chooses PC relative addressing for jump/call labels.

Any instruction that has a memory operand, but no register operand, must specify its size (byte, word, long, or quadruple) with an instruction mnemonic suffix (`b', `w', `l' or `q', respectively).

The x86-64 architecture adds an RIP (instruction pointer relative) addressing. This addressing mode is specified by using `rip' as a base register. Only constant offsets are valid. For example:

AT&T: `1234(%rip)', Intel: `[rip + 1234]'

Points to the address 1234 bytes past the end of the current instruction.

AT&T: `symbol(%rip)', Intel: `[rip + symbol]'

Points to the symbol in RIP relative way, this is shorter than the default absolute addressing.

Other addressing modes remain unchanged in x86-64 architecture, except registers used are 64-bit instead of 32-bit.

8.12.7 Handling of Jump Instructions

Jump instructions are always optimized to use the smallest possible displacements. This is accomplished by using byte (8-bit) displacement jumps whenever the target is sufficiently close. If a byte displacement is insufficient a long displacement is used. We do not support word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump instruction with the `data16' instruction prefix), since the 80386 insists upon masking `%eip' to 16 bits after the word displacement is added. (See also see section 8.12.12 Specifying CPU Architecture)

Note that the `jcxz', `jecxz', `loop', `loopz', `loope', `loopnz' and `loopne' instructions only come in byte displacements, so that if you use these instructions (gcc does not use them) you may get an error message (and incorrect code). The AT&T 80386 assembler tries to get around this problem by expanding `jcxz foo' to

jcxz cx_zero jmp cx_nonzero cx_zero: jmp foo cx_nonzero:

8.12.8 Floating Point

All 80387 floating point types except packed BCD are supported. (BCD support may be added without much difficulty). These data types are 16-, 32-, and 64- bit integers, and single (32-bit), double (64-bit), and extended (80-bit) precision floating point. Each supported type has an instruction mnemonic suffix and a constructor associated with it. Instruction mnemonic suffixes specify the operand's data type. Constructors build these data types into memory.

• Floating point constructors are `.float' or `.single', `.double', and `.tfloat' for 32-, 64-, and 80-bit formats. These correspond to instruction mnemonic suffixes `s', `l', and `t'. `t' stands for 80-bit (ten byte) real. The 80387 only supports this format via the `fldt' (load 80-bit real to stack top) and `fstpt' (store 80-bit real and pop stack) instructions.

• Integer constructors are `.word', `.long' or `.int', and `.quad' for the 16-, 32-, and 64-bit integer formats. The corresponding instruction mnemonic suffixes are `s' (single), `l' (long), and `q' (quad). As with the 80-bit real format, the 64-bit `q' format is only present in the `fildq' (load quad integer to stack top) and `fistpq' (store quad integer and pop stack) instructions.

Register to register operations should not use instruction mnemonic suffixes. `fstl %st, %st(1)' will give a warning, and be assembled as if you wrote `fst %st, %st(1)', since all register to register operations use 80-bit floating point operands. (Contrast this with `fstl %st, mem', which converts `%st' from 80-bit to 64-bit floating point format, then stores the result in the 4 byte location `mem')

8.12.9 Intel's MMX and AMD's 3DNow! SIMD Operations

as supports Intel's MMX instruction set (SIMD instructions for integer data), available on Intel's Pentium MMX processors and Pentium II processors, AMD's K6 and K6-2 processors, Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow! instruction set (SIMD instructions for 32-bit floating point data) available on AMD's K6-2 processor and possibly others in the future.

Currently, as does not support Intel's floating point SIMD, Katmai (KNI).

The eight 64-bit MMX operands, also used by 3DNow!, are called `%mm0', `%mm1', ... `%mm7'. They contain eight 8-bit integers, four 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit floating point values. The MMX registers cannot be used at the same time as the floating point stack.

See Intel and AMD documentation, keeping in mind that the operand order in instructions is reversed from the Intel syntax.

8.12.10 Writing 16-bit Code

While as normally writes only "pure" 32-bit i386 code or 64-bit x86-64 code depending on the default configuration, it also supports writing code to run in real mode or in 16-bit protected mode code segments. To do this, put a `.code16' or `.code16gcc' directive before the assembly language instructions to be run in 16-bit mode. You can switch as back to writing normal 32-bit code with the `.code32' directive.

`.code16gcc' provides experimental support for generating 16-bit code from gcc, and differs from `.code16' in that `call', `ret', `enter', `leave', `push', `pop', `pusha', `popa', `pushf', and `popf' instructions default to 32-bit size. This is so that the stack pointer is manipulated in the same way over function calls, allowing access to function parameters at the same stack offsets as in 32-bit mode. `.code16gcc' also automatically adds address size prefixes where necessary to use the 32-bit addressing modes that gcc generates.

The code which as generates in 16-bit mode will not necessarily run on a 16-bit pre-80386 processor. To write code that runs on such a processor, you must refrain from using any 32-bit constructs which require as to output address or operand size prefixes.

Note that writing 16-bit code instructions by explicitly specifying a prefix or an instruction mnemonic suffix within a 32-bit code section generates different machine instructions than those generated for a 16-bit code segment. In a 32-bit code section, the following code generates the machine opcode bytes `66 6a 04', which pushes the value `4' onto the stack, decrementing `%esp' by 2.

pushw $4

The same code in a 16-bit code section would generate the machine opcode bytes `6a 04' (ie. without the operand size prefix), which is correct since the processor default operand size is assumed to be 16 bits in a 16-bit code section.

8.12.11 AT&T Syntax bugs

The UnixWare assembler, and probably other AT&T derived ix86 Unix assemblers, generate floating point instructions with reversed source and destination registers in certain cases. Unfortunately, gcc and possibly many other programs use this reversed syntax, so we're stuck with it.

For example

fsub %st,%st(3)

results in `%st(3)' being updated to `%st - %st(3)' rather than the expected `%st(3) - %st'. This happens with all the non-commutative arithmetic floating point operations with two register operands where the source register is `%st' and the destination register is `%st(i)'.

8.12.12 Specifying CPU Architecture

as may be told to assemble for a particular CPU architecture with the .arch cpu_type directive. This directive enables a warning when gas detects an instruction that is not supported on the CPU specified. The choices for cpu_type are:

`i8086'	`i186'	`i286'	`i386'
`i486'	`i586'	`i686'	`pentium'
`pentiumpro'	`pentium4'	`k6'	`athlon'
`sledgehammer'

Apart from the warning, there are only two other effects on as operation; Firstly, if you specify a CPU other than `i486', then shift by one instructions such as `sarl $1, %eax' will automatically use a two byte opcode sequence. The larger three byte opcode sequence is used on the 486 (and when no architecture is specified) because it executes faster on the 486. Note that you can explicitly request the two byte opcode by writing `sarl %eax'. Secondly, if you specify `i8086', `i186', or `i286', and `.code16' or `.code16gcc' then byte offset conditional jumps will be promoted when necessary to a two instruction sequence consisting of a conditional jump of the opposite sense around an unconditional jump to the target.

Following the CPU architecture, you may specify `jumps' or `nojumps' to control automatic promotion of conditional jumps. `jumps' is the default, and enables jump promotion; All external jumps will be of the long variety, and file-local jumps will be promoted as necessary. (see section 8.12.7 Handling of Jump Instructions) `nojumps' leaves external conditional jumps as byte offset jumps, and warns about file-local conditional jumps that as promotes. Unconditional jumps are treated as for `jumps'.

For example

.arch i8086,nojumps

8.12.13 Notes

There is some trickery concerning the `mul' and `imul' instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding multiplies (base opcode `0xf6'; extension 4 for `mul' and 5 for `imul') can be output only in the one operand form. Thus, `imul %ebx, %eax' does not select the expanding multiply; the expanding multiply would clobber the `%edx' register, and this would confuse gcc output. Use `imul %ebx' to get the 64-bit product in `%edx:%eax'.

We have added a two operand form of `imul' when the first operand is an immediate mode expression and the second operand is a register. This is just a shorthand, so that, multiplying `%eax' by 69, for example, can be done with `imul $69, %eax' rather than `imul $69, %eax, %eax'.

8.13 Intel i860 Dependent Features

8.13.1 i860 Notes
8.13.2 i860 Command-line Options
8.13.3 i860 Machine Directives
8.13.4 i860 Opcodes

8.13.1 i860 Notes

Like the SVR4/860 assembler, the output object format is ELF32. Currently, this is the only supported object format. If there is sufficient interest, other formats such as COFF may be implemented.

Both the Intel and AT&T/SVR4 syntaxes are supported, with the latter being the default. One difference is that AT&T syntax requires the '%' prefix on register names while Intel syntax does not. Another difference is in the specification of relocatable expressions. The Intel syntax is ha%expression whereas the SVR4 syntax is [expression]@ha (and similarly for the "l" and "h" selectors).

8.13.2 i860 Command-line Options

8.13.2.1 SVR4 compatibility options

-V

Print assembler version.

-Qy

Ignored.

-Qn

Ignored.

8.13.2.2 Other options

-EL

Select little endian output (this is the default).

-EB

Select big endian output. Note that the i860 always reads instructions as little endian data, so this option only effects data and not instructions.

-mwarn-expand

Emit a warning message if any pseudo-instruction expansions occurred. For example, a or instruction with an immediate larger than 16-bits will be expanded into two instructions. This is a very undesirable feature to rely on, so this flag can help detect any code where it happens. One use of it, for instance, has been to find and eliminate any place where gcc may emit these pseudo-instructions.

-mxp

Enable support for the i860XP instructions and control registers. By default, this option is disabled so that only the base instruction set (i.e., i860XR) is supported.

-mintel-syntax

The i860 assembler defaults to AT&T/SVR4 syntax. This option enables the Intel syntax.

8.13.3 i860 Machine Directives

.dual

Enter dual instruction mode. While this directive is supported, the preferred way to use dual instruction mode is to explicitly code the dual bit with the d. prefix.

.enddual

Exit dual instruction mode. While this directive is supported, the preferred way to use dual instruction mode is to explicitly code the dual bit with the d. prefix.

.atmp

Change the temporary register used when expanding pseudo operations. The default register is r31.

The .dual, .enddual, and .atmp directives are available only in the Intel syntax mode.

Both syntaxes allow for the standard .align directive. However, the Intel syntax additionally allows keywords for the alignment parameter: ".align type", where `type' is one of .short, .long, .quad, .single, .double representing alignments of 2, 4, 16, 4, and 8, respectively.

8.13.4 i860 Opcodes

All of the Intel i860XR and i860XP machine instructions are supported. Please see either i860 Microprocessor Programmer's Reference Manual or i860 Microprocessor Architecture for more information.

8.13.4.1 Other instruction support (pseudo-instructions)

• Load large immediate into general register:

  The pseudo-instruction mov imm,%rn (where the immediate does not fit within a signed 16-bit field) will be expanded into:

  orh large_imm@h,%r0,%rn or large_imm@l,%rn,%rn

• Load/store with relocatable address expression:

  For example, the pseudo-instruction ld.b addr_exp(%rx),%rn will be expanded into:

  orh addr_exp@ha,%rx,%r31 ld.l addr_exp@l(%r31),%rn

  The analogous expansions apply to ld.x, st.x, fld.x, pfld.x, fst.x, and pst.x as well.

• Signed large immediate with add/subtract:

  If any of the arithmetic operations adds, addu, subs, subu are used with an immediate larger than 16-bits (signed), then they will be expanded. For instance, the pseudo-instruction adds large_imm,%rx,%rn expands to:

  orh large_imm@h,%r0,%r31 or large_imm@l,%r31,%r31 adds %r31,%rx,%rn

• Unsigned large immediate with logical operations:

  Logical operations (or, andnot, or, xor) also result in expansions. The pseudo-instruction or large_imm,%rx,%rn results in:

  orh large_imm@h,%rx,%r31 or large_imm@l,%r31,%rn

  Similarly for the others, except for and which expands to:

  andnot (-1 - large_imm)@h,%rx,%r31 andnot (-1 - large_imm)@l,%r31,%rn

8.14 Intel 80960 Dependent Features

8.14.1 i960 Command-line Options
8.14.2 Floating Point
8.14.3 i960 Machine Directives
8.14.4 i960 Opcodes

8.14.1 i960 Command-line Options

-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC

Select the 80960 architecture. Instructions or features not supported by the selected architecture cause fatal errors.

`-ACA' is equivalent to `-ACA_A'; `-AKC' is equivalent to `-AMC'. Synonyms are provided for compatibility with other tools.

If you do not specify any of these options, as generates code for any instruction or feature that is supported by some version of the 960 (even if this means mixing architectures!). In principle, as attempts to deduce the minimal sufficient processor type if none is specified; depending on the object code format, the processor type may be recorded in the object file. If it is critical that the as output match a specific architecture, specify that architecture explicitly.

-b

Add code to collect information about conditional branches taken, for later optimization using branch prediction bits. (The conditional branch instructions have branch prediction bits in the CA, CB, and CC architectures.) If BR represents a conditional branch instruction, the following represents the code generated by the assembler when `-b' is specified:

call increment routine .word 0 # pre-counter Label: BR call increment routine .word 0 # post-counter

The counter following a branch records the number of times that branch was not taken; the differenc between the two counters is the number of times the branch was taken.

A table of every such Label is also generated, so that the external postprocessor gbr960 (supplied by Intel) can locate all the counters. This table is always labeled `__BRANCH_TABLE__'; this is a local symbol to permit collecting statistics for many separate object files. The table is word aligned, and begins with a two-word header. The first word, initialized to 0, is used in maintaining linked lists of branch tables. The second word is a count of the number of entries in the table, which follow immediately: each is a word, pointing to one of the labels illustrated above.

+------------+------------+------------+ ... +------------+ | | | | | | | *NEXT | COUNT: N | *BRLAB 1 | | *BRLAB N | | | | | | | +------------+------------+------------+ ... +------------+ __BRANCH_TABLE__ layout

The first word of the header is used to locate multiple branch tables, since each object file may contain one. Normally the links are maintained with a call to an initialization routine, placed at the beginning of each function in the file. The GNU C compiler generates these calls automatically when you give it a `-b' option. For further details, see the documentation of `gbr960'.

-no-relax

Normally, Compare-and-Branch instructions with targets that require displacements greater than 13 bits (or that have external targets) are replaced with the corresponding compare (or `chkbit') and branch instructions. You can use the `-no-relax' option to specify that as should generate errors instead, if the target displacement is larger than 13 bits.

This option does not affect the Compare-and-Jump instructions; the code emitted for them is always adjusted when necessary (depending on displacement size), regardless of whether you use `-no-relax'.

8.14.2 Floating Point

as generates IEEE floating-point numbers for the directives `.float', `.double', `.extended', and `.single'.

8.14.3 i960 Machine Directives

.bss symbol, length, align

Reserve length bytes in the bss section for a local symbol, aligned to the power of two specified by align. length and align must be positive absolute expressions. This directive differs from `.lcomm' only in that it permits you to specify an alignment. See section .lcomm.

.extended flonums

.extended expects zero or more flonums, separated by commas; for each flonum, `.extended' emits an IEEE extended-format (80-bit) floating-point number.

.leafproc call-lab, bal-lab

You can use the `.leafproc' directive in conjunction with the optimized callj instruction to enable faster calls of leaf procedures. If a procedure is known to call no other procedures, you may define an entry point that skips procedure prolog code (and that does not depend on system-supplied saved context), and declare it as the bal-lab using `.leafproc'. If the procedure also has an entry point that goes through the normal prolog, you can specify that entry point as call-lab.

A `.leafproc' declaration is meant for use in conjunction with the optimized call instruction `callj'; the directive records the data needed later to choose between converting the `callj' into a bal or a call.

call-lab is optional; if only one argument is present, or if the two arguments are identical, the single argument is assumed to be the bal entry point.

.sysproc name, index

The `.sysproc' directive defines a name for a system procedure. After you define it using `.sysproc', you can use name to refer to the system procedure identified by index when calling procedures with the optimized call instruction `callj'.

Both arguments are required; index must be between 0 and 31 (inclusive).

8.14.4 i960 Opcodes

All Intel 960 machine instructions are supported; see section i960 Command-line Options for a discussion of selecting the instruction subset for a particular 960 architecture.

Some opcodes are processed beyond simply emitting a single corresponding instruction: `callj', and Compare-and-Branch or Compare-and-Jump instructions with target displacements larger than 13 bits.

8.14.4.1 callj
8.14.4.2 Compare-and-Branch

8.14.4.1 callj

You can write callj to have the assembler or the linker determine the most appropriate form of subroutine call: `call', `bal', or `calls'. If the assembly source contains enough information--a `.leafproc' or `.sysproc' directive defining the operand--then as translates the callj; if not, it simply emits the callj, leaving it for the linker to resolve.

8.14.4.2 Compare-and-Branch

The 960 architectures provide combined Compare-and-Branch instructions that permit you to store the branch target in the lower 13 bits of the instruction word itself. However, if you specify a branch target far enough away that its address won't fit in 13 bits, the assembler can either issue an error, or convert your Compare-and-Branch instruction into separate instructions to do the compare and the branch.

Whether as gives an error or expands the instruction depends on two choices you can make: whether you use the `-no-relax' option, and whether you use a "Compare and Branch" instruction or a "Compare and Jump" instruction. The "Jump" instructions are always expanded if necessary; the "Branch" instructions are expanded when necessary unless you specify -no-relax---in which case as gives an error instead.

These are the Compare-and-Branch instructions, their "Jump" variants, and the instruction pairs they may expand into:

Compare and Branch Jump Expanded to ------ ------ ------------ bbc chkbit; bno bbs chkbit; bo cmpibe cmpije cmpi; be cmpibg cmpijg cmpi; bg cmpibge cmpijge cmpi; bge cmpibl cmpijl cmpi; bl cmpible cmpijle cmpi; ble cmpibno cmpijno cmpi; bno cmpibne cmpijne cmpi; bne cmpibo cmpijo cmpi; bo cmpobe cmpoje cmpo; be cmpobg cmpojg cmpo; bg cmpobge cmpojge cmpo; bge cmpobl cmpojl cmpo; bl cmpoble cmpojle cmpo; ble cmpobne cmpojne cmpo; bne

8.15 IP2K Dependent Features

8.15.1 IP2K Options

8.15.1 IP2K Options

The Ubicom IP2K version of as has a few machine dependent options:

-mip2022ext

as can assemble the extended IP2022 instructions, but it will only do so if this is specifically allowed via this command line option.

-mip2022

This option restores the assembler's default behaviour of not permitting the extended IP2022 instructions to be assembled.

8.16 M32R Dependent Features

8.16.1 M32R Options
8.16.2 M32R Directives
8.16.3 M32R Warnings

8.16.1 M32R Options

The Renease M32R version of as has a few machine dependent options:

-m32rx

as can assemble code for several different members of the Renesas M32R family. Normally the default is to assemble code for the M32R microprocessor. This option may be used to change the default to the M32RX microprocessor, which adds some more instructions to the basic M32R instruction set, and some additional parameters to some of the original instructions.

-m32r2

This option changes the target processor to the the M32R2 microprocessor.

-m32r

This option can be used to restore the assembler's default behaviour of assembling for the M32R microprocessor. This can be useful if the default has been changed by a previous command line option.

-little

This option tells the assembler to produce little-endian code and data. The default is dependent upon how the toolchain was configured.

-EL

This is a synonum for -little.

-big

This option tells the assembler to produce big-endian code and data.

-EB

This is a synonum for -big.

-KPIC

This option specifies that the output of the assembler should be marked as position-independent code (PIC).

-parallel

This option tells the assembler to attempts to combine two sequential instructions into a single, parallel instruction, where it is legal to do so.

-no-parallel

This option disables a previously enabled -parallel option.

-O

This option tells the assembler to attempt to optimize the instructions that it produces. This includes filling delay slots and converting sequential instructions into parallel ones. This option implies -parallel.

-warn-explicit-parallel-conflicts

Instructs as to produce warning messages when questionable parallel instructions are encountered. This option is enabled by default, but gcc disables it when it invokes as directly. Questionable instructions are those whoes behaviour would be different if they were executed sequentially. For example the code fragment `mv r1, r2 || mv r3, r1' produces a different result from `mv r1, r2 \n mv r3, r1' since the former moves r1 into r3 and then r2 into r1, whereas the later moves r2 into r1 and r3.

-Wp

This is a shorter synonym for the -warn-explicit-parallel-conflicts option.

-no-warn-explicit-parallel-conflicts

Instructs as not to produce warning messages when questionable parallel instructions are encountered.

-Wnp

This is a shorter synonym for the -no-warn-explicit-parallel-conflicts option.

-ignore-parallel-conflicts

This option tells the assembler's to stop checking parallel instructions for contraint violations. This ability is provided for hardware vendors testing chip designs and should not be used under normal circumstances.

-no-ignore-parallel-conflicts

This option restores the assembler's default behaviour of checking parallel instructions to detect constraint violations.

-Ip

This is a shorter synonym for the -ignore-parallel-conflicts option.

-nIp

This is a shorter synonym for the -no-ignore-parallel-conflicts option.

-warn-unmatched-high

This option tells the assembler to produce a warning message if a .high pseudo op is encountered without a mathcing .low pseudo op. The presence of such an unmatches pseudo op usually indicates a programming error.

-no-warn-unmatched-high

Disables a previously enabled -warn-unmatched-high option.

-Wuh

This is a shorter synonym for the -warn-unmatched-high option.

-Wnuh

This is a shorter synonym for the -no-warn-unmatched-high option.

8.16.2 M32R Directives

The Renease M32R version of as has a few architecture specific directives:

low expression

The low directive computes the value of its expression and places the lower 16-bits of the result into the immediate-field of the instruction. For example:

or3 r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678 add3, r0, r0, #low(fred) ; compute r0 = r0 + low 16-bits of address of fred

high expression

The high directive computes the value of its expression and places the upper 16-bits of the result into the immediate-field of the instruction. For example:

seth r0, #high(0x12345678) ; compute r0 = 0x12340000 seth, r0, #high(fred) ; compute r0 = upper 16-bits of address of fred

shigh expression

The shigh directive is very similar to the high directive. It also computes the value of its expression and places the upper 16-bits of the result into the immediate-field of the instruction. The difference is that shigh also checks to see if the lower 16-bits could be interpreted as a signed number, and if so it assumes that a borrow will occur from the upper-16 bits. To compensate for this the shigh directive pre-biases the upper 16 bit value by adding one to it. For example:

For example:

seth r0, #shigh(0x12345678) ; compute r0 = 0x12340000 seth r0, #shigh(0x00008000) ; compute r0 = 0x00010000

In the second example the lower 16-bits are 0x8000. If these are treated as a signed value and sign extended to 32-bits then the value becomes 0xffff8000. If this value is then added to 0x00010000 then the result is 0x00008000.

This behaviour is to allow for the different semantics of the or3 and add3 instructions. The or3 instruction treats its 16-bit immediate argument as unsigned whereas the add3 treats its 16-bit immediate as a signed value. So for example:

seth r0, #shigh(0x00008000) add3 r0, r0, #low(0x00008000)

Produces the correct result in r0, whereas:

seth r0, #shigh(0x00008000) or3 r0, r0, #low(0x00008000)

Stores 0xffff8000 into r0.

Note - the shigh directive does not know where in the assembly source code the lower 16-bits of the value are going set, so it cannot check to make sure that an or3 instruction is being used rather than an add3 instruction. It is up to the programmer to make sure that correct directives are used.

.m32r

The directive performs a similar thing as the -m32r command line option. It tells the assembler to only accept M32R instructions from now on. An instructions from later M32R architectures are refused.

.m32rx

The directive performs a similar thing as the -m32rx command line option. It tells the assembler to start accepting the extra instructions in the M32RX ISA as well as the ordinary M32R ISA.

.m32r2

The directive performs a similar thing as the -m32r2 command line option. It tells the assembler to start accepting the extra instructions in the M32R2 ISA as well as the ordinary M32R ISA.

.little

The directive performs a similar thing as the -little command line option. It tells the assembler to start producing little-endian code and data. This option should be used with care as producing mixed-endian binary files is frought with danger.

.big

The directive performs a similar thing as the -big command line option. It tells the assembler to start producing big-endian code and data. This option should be used with care as producing mixed-endian binary files is frought with danger.

8.16.3 M32R Warnings

There are several warning and error messages that can be produced by as which are specific to the M32R:

output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?

This message is only produced if warnings for explicit parallel conflicts have been enabled. It indicates that the assembler has encountered a parallel instruction in which the destination register of the left hand instruction is used as an input register in the right hand instruction. For example in this code fragment `mv r1, r2 || neg r3, r1' register r1 is the destination of the move instruction and the input to the neg instruction.

output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?

This message is only produced if warnings for explicit parallel conflicts have been enabled. It indicates that the assembler has encountered a parallel instruction in which the destination register of the right hand instruction is used as an input register in the left hand instruction. For example in this code fragment `mv r1, r2 || neg r2, r3' register r2 is the destination of the neg instruction and the input to the move instruction.

instruction `...' is for the M32RX only

This message is produced when the assembler encounters an instruction which is only supported by the M32Rx processor, and the `-m32rx' command line flag has not been specified to allow assembly of such instructions.

unknown instruction `...'

This message is produced when the assembler encounters an instruction which it does not recognise.

only the NOP instruction can be issued in parallel on the m32r

This message is produced when the assembler encounters a parallel instruction which does not involve a NOP instruction and the `-m32rx' command line flag has not been specified. Only the M32Rx processor is able to execute two instructions in parallel.

instruction `...' cannot be executed in parallel.

This message is produced when the assembler encounters a parallel instruction which is made up of one or two instructions which cannot be executed in parallel.

Instructions share the same execution pipeline

This message is produced when the assembler encounters a parallel instruction whoes components both use the same execution pipeline.

Instructions write to the same destination register.

This message is produced when the assembler encounters a parallel instruction where both components attempt to modify the same register. For example these code fragments will produce this message: `mv r1, r2 || neg r1, r3' `jl r0 || mv r14, r1' `st r2, @-r1 || mv r1, r3' `mv r1, r2 || ld r0, @r1+' `cmp r1, r2 || addx r3, r4' (Both write to the condition bit)

8.17 M680x0 Dependent Features

8.17.1 M680x0 Options
8.17.2 Syntax
8.17.3 Motorola Syntax
8.17.4 Floating Point
8.17.5 680x0 Machine Directives
8.17.6 Opcodes

8.17.1 M680x0 Options

The Motorola 680x0 version of as has a few machine dependent options:

`-l'

You can use the `-l' option to shorten the size of references to undefined symbols. If you do not use the `-l' option, references to undefined symbols are wide enough for a full long (32 bits). (Since as cannot know where these symbols end up, as can only allocate space for the linker to fill in later. Since as does not know how far away these symbols are, it allocates as much space as it can.) If you use this option, the references are only one word wide (16 bits). This may be useful if you want the object file to be as small as possible, and you know that the relevant symbols are always less than 17 bits away.

`--register-prefix-optional'

For some configurations, especially those where the compiler normally does not prepend an underscore to the names of user variables, the assembler requires a `%' before any use of a register name. This is intended to let the assembler distinguish between C variables and functions named `a0' through `a7', and so on. The `%' is always accepted, but is not required for certain configurations, notably `sun3'. The `--register-prefix-optional' option may be used to permit omitting the `%' even for configurations for which it is normally required. If this is done, it will generally be impossible to refer to C variables and functions with the same names as register names.

`--bitwise-or'

Normally the character `|' is treated as a comment character, which means that it can not be used in expressions. The `--bitwise-or' option turns `|' into a normal character. In this mode, you must either use C style comments, or start comments with a `#' character at the beginning of a line.

`--base-size-default-16 --base-size-default-32'

If you use an addressing mode with a base register without specifying the size, as will normally use the full 32 bit value. For example, the addressing mode `%a0@(%d0)' is equivalent to `%a0@(%d0:l)'. You may use the `--base-size-default-16' option to tell as to default to using the 16 bit value. In this case, `%a0@(%d0)' is equivalent to `%a0@(%d0:w)'. You may use the `--base-size-default-32' option to restore the default behaviour.

`--disp-size-default-16 --disp-size-default-32'

If you use an addressing mode with a displacement, and the value of the displacement is not known, as will normally assume that the value is 32 bits. For example, if the symbol `disp' has not been defined, as will assemble the addressing mode `%a0@(disp,%d0)' as though `disp' is a 32 bit value. You may use the `--disp-size-default-16' option to tell as to instead assume that the displacement is 16 bits. In this case, as will assemble `%a0@(disp,%d0)' as though `disp' is a 16 bit value. You may use the `--disp-size-default-32' option to restore the default behaviour.

`--pcrel'

Always keep branches PC-relative. In the M680x0 architecture all branches are defined as PC-relative. However, on some processors they are limited to word displacements maximum. When as needs a long branch that is not available, it normally emits an absolute jump instead. This option disables this substitution. When this option is given and no long branches are available, only word branches will be emitted. An error message will be generated if a word branch cannot reach its target. This option has no effect on 68020 and other processors that have long branches. see section Branch Improvement.

`-m68000'

as can assemble code for several different members of the Motorola 680x0 family. The default depends upon how as was configured when it was built; normally, the default is to assemble code for the 68020 microprocessor. The following options may be used to change the default. These options control which instructions and addressing modes are permitted. The members of the 680x0 family are very similar. For detailed information about the differences, see the Motorola manuals.

`-m68000'

`-m68ec000'

`-m68hc000'

`-m68hc001'

`-m68008'

`-m68302'

`-m68306'

`-m68307'

`-m68322'

`-m68356'

Assemble for the 68000. `-m68008', `-m68302', and so on are synonyms for `-m68000', since the chips are the same from the point of view of the assembler.

`-m68010'

Assemble for the 68010.

`-m68020'

`-m68ec020'

Assemble for the 68020. This is normally the default.

`-m68030'

`-m68ec030'

Assemble for the 68030.

`-m68040'

`-m68ec040'

Assemble for the 68040.

`-m68060'

`-m68ec060'

Assemble for the 68060.

`-mcpu32'

`-m68330'

`-m68331'

`-m68332'

`-m68333'

`-m68334'

`-m68336'

`-m68340'

`-m68341'

`-m68349'

`-m68360'

Assemble for the CPU32 family of chips.

`-m5200'

`-m5202'

`-m5204'

`-m5206'

`-m5206e'

`-m528x'

`-m5307'

`-m5407'

`-mcfv4'

`-mcfv4e'

Assemble for the ColdFire family of chips.

`-m68881'

`-m68882'

Assemble 68881 floating point instructions. This is the default for the 68020, 68030, and the CPU32. The 68040 and 68060 always support floating point instructions.

`-mno-68881'

Do not assemble 68881 floating point instructions. This is the default for 68000 and the 68010. The 68040 and 68060 always support floating point instructions, even if this option is used.

`-m68851'

Assemble 68851 MMU instructions. This is the default for the 68020, 68030, and 68060. The 68040 accepts a somewhat different set of MMU instructions; `-m68851' and `-m68040' should not be used together.

`-mno-68851'

Do not assemble 68851 MMU instructions. This is the default for the 68000, 68010, and the CPU32. The 68040 accepts a somewhat different set of MMU instructions.

8.17.2 Syntax

This syntax for the Motorola 680x0 was developed at MIT.

The 680x0 version of as uses instructions names and syntax compatible with the Sun assembler. Intervening periods are ignored; for example, `movl' is equivalent to `mov.l'.

In the following table apc stands for any of the address registers (`%a0' through `%a7'), the program counter (`%pc'), the zero-address relative to the program counter (`%zpc'), a suppressed address register (`%za0' through `%za7'), or it may be omitted entirely. The use of size means one of `w' or `l', and it may be omitted, along with the leading colon, unless a scale is also specified. The use of scale means one of `1', `2', `4', or `8', and it may always be omitted along with the leading colon.

The following addressing modes are understood:

Immediate

`#number'

Data Register

`%d0' through `%d7'

Address Register

`%a0' through `%a7'
`%a7' is also known as `%sp', i.e. the Stack Pointer. %a6 is also known as `%fp', the Frame Pointer.

Address Register Indirect

`%a0@' through `%a7@'

Address Register Postincrement

`%a0@+' through `%a7@+'

Address Register Predecrement

`%a0@-' through `%a7@-'

Indirect Plus Offset

`apc@(number)'

Index

`apc@(number,register:size:scale)'

The number may be omitted.

Postindex

`apc@(number)@(onumber,register:size:scale)'

The onumber or the register, but not both, may be omitted.

Preindex

`apc@(number,register:size:scale)@(onumber)'

The number may be omitted. Omitting the register produces the Postindex addressing mode.

Absolute

`symbol', or `digits', optionally followed by `:b', `:w', or `:l'.

8.17.3 Motorola Syntax

The standard Motorola syntax for this chip differs from the syntax already discussed (see section Syntax). as can accept Motorola syntax for operands, even if MIT syntax is used for other operands in the same instruction. The two kinds of syntax are fully compatible.

In the following table apc stands for any of the address registers (`%a0' through `%a7'), the program counter (`%pc'), the zero-address relative to the program counter (`%zpc'), or a suppressed address register (`%za0' through `%za7'). The use of size means one of `w' or `l', and it may always be omitted along with the leading dot. The use of scale means one of `1', `2', `4', or `8', and it may always be omitted along with the leading asterisk.

The following additional addressing modes are understood:

Address Register Indirect

`(%a0)' through `(%a7)'
`%a7' is also known as `%sp', i.e. the Stack Pointer. %a6 is also known as `%fp', the Frame Pointer.

Address Register Postincrement

`(%a0)+' through `(%a7)+'

Address Register Predecrement

`-(%a0)' through `-(%a7)'

Indirect Plus Offset

`number(%a0)' through `number(%a7)', or `number(%pc)'.

The number may also appear within the parentheses, as in `(number,%a0)'. When used with the pc, the number may be omitted (with an address register, omitting the number produces Address Register Indirect mode).

Index

`number(apc,register.size*scale)'

The number may be omitted, or it may appear within the parentheses. The apc may be omitted. The register and the apc may appear in either order. If both apc and register are address registers, and the size and scale are omitted, then the first register is taken as the base register, and the second as the index register.

Postindex

`([number,apc],register.size*scale,onumber)'

The onumber, or the register, or both, may be omitted. Either the number or the apc may be omitted, but not both.

Preindex

`([number,apc,register.size*scale],onumber)'

The number, or the apc, or the register, or any two of them, may be omitted. The onumber may be omitted. The register and the apc may appear in either order. If both apc and register are address registers, and the size and scale are omitted, then the first register is taken as the base register, and the second as the index register.

8.17.4 Floating Point

Packed decimal (P) format floating literals are not supported. Feel free to add the code!

The floating point formats generated by directives are these.

.float

Single precision floating point constants.

.double

Double precision floating point constants.

.extend

.ldouble

Extended precision (long double) floating point constants.

8.17.5 680x0 Machine Directives

In order to be compatible with the Sun assembler the 680x0 assembler understands the following directives.

.data1

This directive is identical to a .data 1 directive.

.data2

This directive is identical to a .data 2 directive.

.even

This directive is a special case of the .align directive; it aligns the output to an even byte boundary.

.skip

This directive is identical to a .space directive.

8.17.6 Opcodes

8.17.6.1 Branch Improvement
8.17.6.2 Special Characters

8.17.6.1 Branch Improvement

Certain pseudo opcodes are permitted for branch instructions. They expand to the shortest branch instruction that reach the target. Generally these mnemonics are made by substituting `j' for `b' at the start of a Motorola mnemonic.

The following table summarizes the pseudo-operations. A * flags cases that are more fully described after the table:

Displacement +------------------------------------------------------------ | 68020 68000/10, not PC-relative OK Pseudo-Op |BYTE WORD LONG ABSOLUTE LONG JUMP ** +------------------------------------------------------------ jbsr |bsrs bsrw bsrl jsr jra |bras braw bral jmp * jXX |bXXs bXXw bXXl bNXs;jmp * dbXX | N/A dbXXw dbXX;bras;bral dbXX;bras;jmp fjXX | N/A fbXXw fbXXl N/A XX: condition NX: negative of condition XX

jbsr

jra

These are the simplest jump pseudo-operations; they always map to one particular machine instruction, depending on the displacement to the branch target. This instruction will be a byte or word branch is that is sufficient. Otherwise, a long branch will be emitted if available. If no long branches are available and the `--pcrel' option is not given, an absolute long jump will be emitted instead. If no long branches are available, the `--pcrel' option is given, and a word branch cannot reach the target, an error message is generated.

In addition to standard branch operands, as allows these pseudo-operations to have all operands that are allowed for jsr and jmp, substituting these instructions if the operand given is not valid for a branch instruction.

jXX

Here, `jXX' stands for an entire family of pseudo-operations, where XX is a conditional branch or condition-code test. The full list of pseudo-ops in this family is:

jhi jls jcc jcs jne jeq jvc jvs jpl jmi jge jlt jgt jle

Usually, each of these pseudo-operations expands to a single branch instruction. However, if a word branch is not sufficient, no long branches are available, and the `--pcrel' option is not given, as issues a longer code fragment in terms of NX, the opposite condition to XX. For example, under these conditions:

jXX foo

gives

bNXs oof jmp foo oof:

dbXX

The full family of pseudo-operations covered here is

dbhi dbls dbcc dbcs dbne dbeq dbvc dbvs dbpl dbmi dbge dblt dbgt dble dbf dbra dbt

Motorola `dbXX' instructions allow word displacements only. When a word displacement is sufficient, each of these pseudo-operations expands to the corresponding Motorola instruction. When a word displacement is not sufficient and long branches are available, when the source reads `dbXX foo', as emits

dbXX oo1 bras oo2 oo1:bral foo oo2:

If, however, long branches are not available and the `--pcrel' option is not given, as emits

dbXX oo1 bras oo2 oo1:jmp foo oo2:

fjXX

This family includes

fjne fjeq fjge fjlt fjgt fjle fjf fjt fjgl fjgle fjnge fjngl fjngle fjngt fjnle fjnlt fjoge fjogl fjogt fjole fjolt fjor fjseq fjsf fjsne fjst fjueq fjuge fjugt fjule fjult fjun

Each of these pseudo-operations always expands to a single Motorola coprocessor branch instruction, word or long. All Motorola coprocessor branch instructions allow both word and long displacements.

8.17.6.2 Special Characters

The immediate character is `#' for Sun compatibility. The line-comment character is `|' (unless the `--bitwise-or' option is used). If a `#' appears at the beginning of a line, it is treated as a comment unless it looks like `# line file', in which case it is treated normally.

8.18 M68HC11 and M68HC12 Dependent Features

8.18.1 M68HC11 and M68HC12 Options
8.18.2 Syntax
8.18.3 Symbolic Operand Modifiers
8.18.4 Assembler Directives
8.18.5 Floating Point
8.18.6 Opcodes

8.18.1 M68HC11 and M68HC12 Options

The Motorola 68HC11 and 68HC12 version of as have a few machine dependent options.

-m68hc11

This option switches the assembler in the M68HC11 mode. In this mode, the assembler only accepts 68HC11 operands and mnemonics. It produces code for the 68HC11.

-m68hc12

This option switches the assembler in the M68HC12 mode. In this mode, the assembler also accepts 68HC12 operands and mnemonics. It produces code for the 68HC12. A few 68HC11 instructions are replaced by some 68HC12 instructions as recommended by Motorola specifications.

-m68hcs12

This option switches the assembler in the M68HCS12 mode. This mode is similar to `-m68hc12' but specifies to assemble for the 68HCS12 series. The only difference is on the assembling of the `movb' and `movw' instruction when a PC-relative operand is used.

-mshort

This option controls the ABI and indicates to use a 16-bit integer ABI. It has no effect on the assembled instructions. This is the default.

-mlong

This option controls the ABI and indicates to use a 32-bit integer ABI.

-mshort-double

This option controls the ABI and indicates to use a 32-bit float ABI. This is the default.

-mlong-double

This option controls the ABI and indicates to use a 64-bit float ABI.

--strict-direct-mode

You can use the `--strict-direct-mode' option to disable the automatic translation of direct page mode addressing into extended mode when the instruction does not support direct mode. For example, the `clr' instruction does not support direct page mode addressing. When it is used with the direct page mode, as will ignore it and generate an absolute addressing. This option prevents as from doing this, and the wrong usage of the direct page mode will raise an error.

--short-branchs

The `--short-branchs' option turns off the translation of relative branches into absolute branches when the branch offset is out of range. By default as transforms the relative branch (`bsr', `bgt', `bge', `beq', `bne', `ble', `blt', `bhi', `bcc', `bls', `bcs', `bmi', `bvs', `bvs', `bra') into an absolute branch when the offset is out of the -128 .. 127 range. In that case, the `bsr' instruction is translated into a `jsr', the `bra' instruction is translated into a `jmp' and the conditional branchs instructions are inverted and followed by a `jmp'. This option disables these translations and as will generate an error if a relative branch is out of range. This option does not affect the optimization associated to the `jbra', `jbsr' and `jbXX' pseudo opcodes.

--force-long-branchs

The `--force-long-branchs' option forces the translation of relative branches into absolute branches. This option does not affect the optimization associated to the `jbra', `jbsr' and `jbXX' pseudo opcodes.

--print-insn-syntax

You can use the `--print-insn-syntax' option to obtain the syntax description of the instruction when an error is detected.

--print-opcodes

The `--print-opcodes' option prints the list of all the instructions with their syntax. The first item of each line represents the instruction name and the rest of the line indicates the possible operands for that instruction. The list is printed in alphabetical order. Once the list is printed as exits.

--generate-example

The `--generate-example' option is similar to `--print-opcodes' but it generates an example for each instruction instead.

8.18.2 Syntax

In the M68HC11 syntax, the instruction name comes first and it may be followed by one or several operands (up to three). Operands are separated by comma (`,'). In the normal mode, as will complain if too many operands are specified for a given instruction. In the MRI mode (turned on with `-M' option), it will treat them as comments. Example:

inx lda #23 bset 2,x #4 brclr *bot #8 foo

The following addressing modes are understood for 68HC11 and 68HC12:

Immediate

`#number'

Address Register

`number,X', `number,Y'

The number may be omitted in which case 0 is assumed.

Direct Addressing mode

`*symbol', or `*digits'

Absolute

`symbol', or `digits'

The M68HC12 has other more complex addressing modes. All of them are supported and they are represented below:

Constant Offset Indexed Addressing Mode

`number,reg'

The number may be omitted in which case 0 is assumed. The register can be either `X', `Y', `SP' or `PC'. The assembler will use the smaller post-byte definition according to the constant value (5-bit constant offset, 9-bit constant offset or 16-bit constant offset). If the constant is not known by the assembler it will use the 16-bit constant offset post-byte and the value will be resolved at link time.

Offset Indexed Indirect

`[number,reg]'

The register can be either `X', `Y', `SP' or `PC'.

Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement

`number,-reg' `number,+reg' `number,reg-' `number,reg+'

The number must be in the range `-8'..`+8' and must not be 0. The register can be either `X', `Y', `SP' or `PC'.

Accumulator Offset

`acc,reg'

The accumulator register can be either `A', `B' or `D'. The register can be either `X', `Y', `SP' or `PC'.

Accumulator D offset indexed-indirect

`[D,reg]'

The register can be either `X', `Y', `SP' or `PC'.

For example:

ldab 1024,sp ldd [10,x] orab 3,+x stab -2,y- ldx a,pc sty [d,sp]

8.18.3 Symbolic Operand Modifiers

The assembler supports several modifiers when using symbol addresses in 68HC11 and 68HC12 instruction operands. The general syntax is the following:

%modifier(symbol)

%addr

This modifier indicates to the assembler and linker to use the 16-bit physical address corresponding to the symbol. This is intended to be used on memory window systems to map a symbol in the memory bank window. If the symbol is in a memory expansion part, the physical address corresponds to the symbol address within the memory bank window. If the symbol is not in a memory expansion part, this is the symbol address (using or not using the %addr modifier has no effect in that case).

%page

This modifier indicates to use the memory page number corresponding to the symbol. If the symbol is in a memory expansion part, its page number is computed by the linker as a number used to map the page containing the symbol in the memory bank window. If the symbol is not in a memory expansion part, the page number is 0.

%hi

This modifier indicates to use the 8-bit high part of the physical address of the symbol.

%lo

This modifier indicates to use the 8-bit low part of the physical address of the symbol.

For example a 68HC12 call to a function `foo_example' stored in memory expansion part could be written as follows:

call %addr(foo_example),%page(foo_example)

and this is equivalent to

call foo_example

And for 68HC11 it could be written as follows:

ldab #%page(foo_example) stab _page_switch jsr %addr(foo_example)

8.18.4 Assembler Directives

The 68HC11 and 68HC12 version of as have the following specific assembler directives:

.relax

The relax directive is used by the `GNU Compiler' to emit a specific relocation to mark a group of instructions for linker relaxation. The sequence of instructions within the group must be known to the linker so that relaxation can be performed.

.mode [mshort|mlong|mshort-double|mlong-double]

This directive specifies the ABI. It overrides the `-mshort', `-mlong', `-mshort-double' and `-mlong-double' options.

.far symbol

This directive marks the symbol as a `far' symbol meaning that it uses a `call/rtc' calling convention as opposed to `jsr/rts'. During a final link, the linker will identify references to the `far' symbol and will verify the proper calling convention.

.interrupt symbol

This directive marks the symbol as an interrupt entry point. This information is then used by the debugger to correctly unwind the frame across interrupts.

.xrefb symbol

This directive is defined for compatibility with the `Specification for Motorola 8 and 16-Bit Assembly Language Input Standard' and is ignored.

8.18.5 Floating Point

Packed decimal (P) format floating literals are not supported. Feel free to add the code!

The floating point formats generated by directives are these.

.float

Single precision floating point constants.

.double

Double precision floating point constants.

.extend

.ldouble

Extended precision (long double) floating point constants.

8.18.6 Opcodes

8.18.6.1 Branch Improvement

8.18.6.1 Branch Improvement

Certain pseudo opcodes are permitted for branch instructions. They expand to the shortest branch instruction that reach the target. Generally these mnemonics are made by prepending `j' to the start of Motorola mnemonic. These pseudo opcodes are not affected by the `--short-branchs' or `--force-long-branchs' options.

The following table summarizes the pseudo-operations.

Displacement Width +-------------------------------------------------------------+ | Options | | --short-branchs --force-long-branchs | +--------------------------+----------------------------------+ Op |BYTE WORD | BYTE WORD | +--------------------------+----------------------------------+ bsr | bsr <pc-rel> <error> | jsr <abs> | bra | bra <pc-rel> <error> | jmp <abs> | jbsr | bsr <pc-rel> jsr <abs> | bsr <pc-rel> jsr <abs> | jbra | bra <pc-rel> jmp <abs> | bra <pc-rel> jmp <abs> | bXX | bXX <pc-rel> <error> | bNX +3; jmp <abs> | jbXX | bXX <pc-rel> bNX +3; | bXX <pc-rel> bNX +3; jmp <abs> | | jmp <abs> | | +--------------------------+----------------------------------+ XX: condition NX: negative of condition XX

jbsr

jbra

These are the simplest jump pseudo-operations; they always map to one particular machine instruction, depending on the displacement to the branch target.

jbXX

Here, `jbXX' stands for an entire family of pseudo-operations, where XX is a conditional branch or condition-code test. The full list of pseudo-ops in this family is:

jbcc jbeq jbge jbgt jbhi jbvs jbpl jblo jbcs jbne jblt jble jbls jbvc jbmi

For the cases of non-PC relative displacements and long displacements, as issues a longer code fragment in terms of NX, the opposite condition to XX. For example, for the non-PC relative case:

jbXX foo

gives

bNXs oof jmp foo oof:

8.19 Motorola M88K Dependent Features

8.19.1 M88K Machine Directives

8.19.1 M88K Machine Directives

The M88K version of the assembler supports the following machine directives:

.align

This directive aligns the section program counter on the next 4-byte boundary.

.dfloat expr

This assembles a double precision (64-bit) floating point constant.

.ffloat expr

This assembles a single precision (32-bit) floating point constant.

.half expr

This directive assembles a half-word (16-bit) constant.

.word expr

This assembles a word (32-bit) constant.

.string "str"

This directive behaves like the standard .ascii directive for copying str into the object file. The string is not terminated with a null byte.

.set symbol, value

This directive creates a symbol named symbol which is an alias for another symbol (possibly not yet defined). This should not be confused with the mnemonic set, which is a legitimate M88K instruction.

.def symbol, value

This directive is synonymous with .set and is presumably provided for compatibility with other M88K assemblers.

.bss symbol, length, align

Reserve length bytes in the bss section for a local symbol, aligned to the power of two specified by align. length and align must be positive absolute expressions. This directive differs from `.lcomm' only in that it permits you to specify an alignment. See section .lcomm.

8.20 MIPS Dependent Features

GNU as for MIPS architectures supports several different MIPS processors, and MIPS ISA levels I through V, MIPS32, and MIPS64. For information about the MIPS instruction set, see MIPS RISC Architecture, by Kane and Heindrich (Prentice-Hall). For an overview of MIPS assembly conventions, see "Appendix D: Assembly Language Programming" in the same work.

8.20.1 Assembler options
8.20.2 MIPS ECOFF object code		ECOFF object code
8.20.3 Directives for debugging information
8.20.4 Directives to override the ISA level
8.20.5 Directives for extending MIPS 16 bit instructions
8.20.6 Directive to mark data as an instruction
8.20.7 Directives to save and restore options
8.20.8 Directives to control generation of MIPS ASE instructions

8.20.1 Assembler options

The MIPS configurations of GNU as support these special options:

-G num

This option sets the largest size of an object that can be referenced implicitly with the gp register. It is only accepted for targets that use ECOFF format. The default value is 8.

-EB

-EL

Any MIPS configuration of as can select big-endian or little-endian output at run time (unlike the other GNU development tools, which must be configured for one or the other). Use `-EB' to select big-endian output, and `-EL' for little-endian.

-mips1

-mips2

-mips3

-mips4

-mips5

-mips32

-mips32r2

-mips64

-mips64r2

Generate code for a particular MIPS Instruction Set Architecture level. `-mips1' corresponds to the R2000 and R3000 processors, `-mips2' to the R6000 processor, `-mips3' to the R4000 processor, and `-mips4' to the R8000 and R10000 processors. `-mips5', `-mips32', `-mips32r2', `-mips64', and `-mips64r2' correspond to generic MIPS V, MIPS32, MIPS32 RELEASE 2, MIPS64, and MIPS64 RELEASE 2 ISA processors, respectively. You can also switch instruction sets during the assembly; see Directives to override the ISA level.

-mgp32

-mfp32

Some macros have different expansions for 32-bit and 64-bit registers. The register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 32 bits wide at all times. `-mgp32' controls the size of general-purpose registers and `-mfp32' controls the size of floating-point registers.

On some MIPS variants there is a 32-bit mode flag; when this flag is set, 64-bit instructions generate a trap. Also, some 32-bit OSes only save the 32-bit registers on a context switch, so it is essential never to use the 64-bit registers.

-mgp64

Assume that 64-bit general purpose registers are available. This is provided in the interests of symmetry with -gp32.

-mips16

-no-mips16

Generate code for the MIPS 16 processor. This is equivalent to putting `.set mips16' at the start of the assembly file. `-no-mips16' turns off this option.

-mips3d

-no-mips3d

Generate code for the MIPS-3D Application Specific Extension. This tells the assembler to accept MIPS-3D instructions. `-no-mips3d' turns off this option.

-mdmx

-no-mdmx

Generate code for the MDMX Application Specific Extension. This tells the assembler to accept MDMX instructions. `-no-mdmx' turns off this option.

-mfix7000

-mno-fix7000

Cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions.

-mfix-vr4120

-no-mfix-vr4120

Insert nops to work around certain VR4120 errata. This option is intended to be used on GCC-generated code: it is not designed to catch all problems in hand-written assembler code.

-m4010

-no-m4010

Generate code for the LSI R4010 chip. This tells the assembler to accept the R4010 specific instructions (`addciu', `ffc', etc.), and to not schedule `nop' instructions around accesses to the `HI' and `LO' registers. `-no-m4010' turns off this option.

-m4650

-no-m4650

Generate code for the MIPS R4650 chip. This tells the assembler to accept the `mad' and `madu' instruction, and to not schedule `nop' instructions around accesses to the `HI' and `LO' registers. `-no-m4650' turns off this option.

-m3900

-no-m3900

-m4100

-no-m4100

For each option `-mnnnn', generate code for the MIPS RNNNN chip. This tells the assembler to accept instructions specific to that chip, and to schedule for that chip's hazards.

-march=cpu

Generate code for a particular MIPS cpu. It is exactly equivalent to `-mcpu', except that there are more value of cpu understood. Valid cpu value are:

2000, 3000, 3900, 4000, 4010, 4100, 4111, vr4120, vr4130, vr4181, 4300, 4400, 4600, 4650, 5000, rm5200, rm5230, rm5231, rm5261, rm5721, vr5400, vr5500, 6000, rm7000, 8000, rm9000, 10000, 12000, mips32-4k, sb1

-mtune=cpu

Schedule and tune for a particular MIPS cpu. Valid cpu values are identical to `-march=cpu'.

-mabi=abi

Record which ABI the source code uses. The recognized arguments are: `32', `n32', `o64', `64' and `eabi'.

-nocpp

This option is ignored. It is accepted for command-line compatibility with other assemblers, which use it to turn off C style preprocessing. With GNU as, there is no need for `-nocpp', because the GNU assembler itself never runs the C preprocessor.

--construct-floats

--no-construct-floats

The --no-construct-floats option disables the construction of double width floating point constants by loading the two halves of the value into the two single width floating point registers that make up the double width register. This feature is useful if the processor support the FR bit in its status register, and this bit is known (by the programmer) to be set. This bit prevents the aliasing of the double width register by the single width registers.

By default --construct-floats is selected, allowing construction of these floating point constants.

--trap

--no-break

as automatically macro expands certain division and multiplication instructions to check for overflow and division by zero. This option causes as to generate code to take a trap exception rather than a break exception when an error is detected. The trap instructions are only supported at Instruction Set Architecture level 2 and higher.

--break

--no-trap

Generate code to take a break exception rather than a trap exception when an error is detected. This is the default.

-mpdr

-mno-pdr

Control generation of .pdr sections. Off by default on IRIX, on elsewhere.

8.20.2 MIPS ECOFF object code

Assembling for a MIPS ECOFF target supports some additional sections besides the usual .text, .data and .bss. The additional sections are .rdata, used for read-only data, .sdata, used for small data, and .sbss, used for small common objects.

When assembling for ECOFF, the assembler uses the $gp ($28) register to form the address of a "small object". Any object in the .sdata or .sbss sections is considered "small" in this sense. For external objects, or for objects in the .bss section, you can use the gcc `-G' option to control the size of objects addressed via $gp; the default value is 8, meaning that a reference to any object eight bytes or smaller uses $gp. Passing `-G 0' to as prevents it from using the $gp register on the basis of object size (but the assembler uses $gp for objects in .sdata or sbss in any case). The size of an object in the .bss section is set by the .comm or .lcomm directive that defines it. The size of an external object may be set with the .extern directive. For example, `.extern sym,4' declares that the object at sym is 4 bytes in length, whie leaving sym otherwise undefined.

Using small ECOFF objects requires linker support, and assumes that the $gp register is correctly initialized (normally done automatically by the startup code). MIPS ECOFF assembly code must not modify the $gp register.

8.20.3 Directives for debugging information

MIPS ECOFF as supports several directives used for generating debugging information which are not support by traditional MIPS assemblers. These are .def, .endef, .dim, .file, .scl, .size, .tag, .type, .val, .stabd, .stabn, and .stabs. The debugging information generated by the three .stab directives can only be read by GDB, not by traditional MIPS debuggers (this enhancement is required to fully support C++ debugging). These directives are primarily used by compilers, not assembly language programmers!

8.20.4 Directives to override the ISA level

GNU as supports an additional directive to change the MIPS Instruction Set Architecture level on the fly: .set mipsn. n should be a number from 0 to 5, or 32, 32r2, 64 or 64r2. The values other than 0 make the assembler accept instructions for the corresponding ISA level, from that point on in the assembly. .set mipsn affects not only which instructions are permitted, but also how certain macros are expanded. .set mips0 restores the ISA level to its original level: either the level you selected with command line options, or the default for your configuration. You can use this feature to permit specific R4000 instructions while assembling in 32 bit mode. Use this directive with care!

The directive `.set mips16' puts the assembler into MIPS 16 mode, in which it will assemble instructions for the MIPS 16 processor. Use `.set nomips16' to return to normal 32 bit mode.

Traditional MIPS assemblers do not support this directive.

8.20.5 Directives for extending MIPS 16 bit instructions

By default, MIPS 16 instructions are automatically extended to 32 bits when necessary. The directive `.set noautoextend' will turn this off. When `.set noautoextend' is in effect, any 32 bit instruction must be explicitly extended with the `.e' modifier (e.g., `li.e $4,1000'). The directive `.set autoextend' may be used to once again automatically extend instructions when necessary.

This directive is only meaningful when in MIPS 16 mode. Traditional MIPS assemblers do not support this directive.

8.20.6 Directive to mark data as an instruction

The .insn directive tells as that the following data is actually instructions. This makes a difference in MIPS 16 mode: when loading the address of a label which precedes instructions, as automatically adds 1 to the value, so that jumping to the loaded address will do the right thing.

8.20.7 Directives to save and restore options

The directives .set push and .set pop may be used to save and restore the current settings for all the options which are controlled by .set. The .set push directive saves the current settings on a stack. The .set pop directive pops the stack and restores the settings.

These directives can be useful inside an macro which must change an option such as the ISA level or instruction reordering but does not want to change the state of the code which invoked the macro.

Traditional MIPS assemblers do not support these directives.

8.20.8 Directives to control generation of MIPS ASE instructions

The directive .set mips3d makes the assembler accept instructions from the MIPS-3D Application Specific Extension from that point on in the assembly. The .set nomips3d directive prevents MIPS-3D instructions from being accepted.

The directive .set mdmx makes the assembler accept instructions from the MDMX Application Specific Extension from that point on in the assembly. The .set nomdmx directive prevents MDMX instructions from being accepted.

Traditional MIPS assemblers do not support these directives.

8.21 MMIX Dependent Features

8.21.1 Command-line Options
8.21.2 Instruction expansion
8.21.3 Syntax
8.21.4 Differences to mmixal		Differences to mmixal syntax and semantics

8.21.1 Command-line Options

The MMIX version of as has some machine-dependent options.

When `--fixed-special-register-names' is specified, only the register names specified in 8.21.3.3 Register names are recognized in the instructions PUT and GET.

You can use the `--globalize-symbols' to make all symbols global. This option is useful when splitting up a mmixal program into several files.

The `--gnu-syntax' turns off most syntax compatibility with mmixal. Its usability is currently doubtful.

The `--relax' option is not fully supported, but will eventually make the object file prepared for linker relaxation.

If you want to avoid inadvertently calling a predefined symbol and would rather get an error, for example when using as with a compiler or other machine-generated code, specify `--no-predefined-syms'. This turns off built-in predefined definitions of all such symbols, including rounding-mode symbols, segment symbols, `BIT' symbols, and TRAP symbols used in mmix "system calls". It also turns off predefined special-register names, except when used in PUT and GET instructions.

By default, some instructions are expanded to fit the size of the operand or an external symbol (see section 8.21.2 Instruction expansion). By passing `--no-expand', no such expansion will be done, instead causing errors at link time if the operand does not fit.

The mmixal documentation (see mmixsite) specifies that global registers allocated with the `GREG' directive (see MMIX-greg) and initialized to the same non-zero value, will refer to the same global register. This isn't strictly enforceable in as since the final addresses aren't known until link-time, but it will do an effort unless the `--no-merge-gregs' option is specified. (Register merging isn't yet implemented in ld.)

as will warn every time it expands an instruction to fit an operand unless the option `-x' is specified. It is believed that this behaviour is more useful than just mimicking mmixal's behaviour, in which instructions are only expanded if the `-x' option is specified, and assembly fails otherwise, when an instruction needs to be expanded. It needs to be kept in mind that mmixal is both an assembler and linker, while as will expand instructions that at link stage can be contracted. (Though linker relaxation isn't yet implemented in ld.) The option `-x' also imples `--linker-allocated-gregs'.

If instruction expansion is enabled, as can expand a `PUSHJ' instruction into a series of instructions. The shortest expansion is to not expand it, but just mark the call as redirectable to a stub, which ld creates at link-time, but only if the original `PUSHJ' instruction is found not to reach the target. The stub consists of the necessary instructions to form a jump to the target. This happens if as can assert that the `PUSHJ' instruction can reach such a stub. The option `--no-pushj-stubs' disables this shorter expansion, and the longer series of instructions is then created at assembly-time. The option `--no-stubs' is a synonym, intended for compatibility with future releases, where generation of stubs for other instructions may be implemented.

Usually a two-operand-expression (see GREG-base) without a matching `GREG' directive is treated as an error by as. When the option `--linker-allocated-gregs' is in effect, they are instead passed through to the linker, which will allocate as many global registers as is needed.

8.21.2 Instruction expansion

When as encounters an instruction with an operand that is either not known or does not fit the operand size of the instruction, as (and ld) will expand the instruction into a sequence of instructions semantically equivalent to the operand fitting the instruction. Expansion will take place for the following instructions:

`GETA'

Expands to a sequence of four instructions: SETL, INCML, INCMH and INCH. The operand must be a multiple of four.

Conditional branches

A branch instruction is turned into a branch with the complemented condition and prediction bit over five instructions; four instructions setting $255 to the operand value, which like with GETA must be a multiple of four, and a final GO $255,$255,0.

`PUSHJ'

Similar to expansion for conditional branches; four instructions set $255 to the operand value, followed by a PUSHGO $255,$255,0.

`JMP'

Similar to conditional branches and PUSHJ. The final instruction is GO $255,$255,0.

The linker ld is expected to shrink these expansions for code assembled with `--relax' (though not currently implemented).

8.21.3 Syntax

The assembly syntax is supposed to be upward compatible with that described in Sections 1.3 and 1.4 of `The Art of Computer Programming, Volume 1'. Draft versions of those chapters as well as other MMIX information is located at http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html. Most code examples from the mmixal package located there should work unmodified when assembled and linked as single files, with a few noteworthy exceptions (see section 8.21.4 Differences to mmixal).

Before an instruction is emitted, the current location is aligned to the next four-byte boundary. If a label is defined at the beginning of the line, its value will be the aligned value.

In addition to the traditional hex-prefix `0x', a hexadecimal number can also be specified by the prefix character `#'.

After all operands to an MMIX instruction or directive have been specified, the rest of the line is ignored, treated as a comment.

8.21.3.1 Special Characters
8.21.3.2 Symbols
8.21.3.3 Register names		Register Names
8.21.3.4 Assembler Directives

8.21.3.1 Special Characters

The characters `*' and `#' are line comment characters; each start a comment at the beginning of a line, but only at the beginning of a line. A `#' prefixes a hexadecimal number if found elsewhere on a line.

Two other characters, `%' and `!', each start a comment anywhere on the line. Thus you can't use the `modulus' and `not' operators in expressions normally associated with these two characters.

A `;' is a line separator, treated as a new-line, so separate instructions can be specified on a single line.

8.21.3.2 Symbols

The character `@' in an expression, is a synonym for `.', the current location.

In addition to the common forward and backward local symbol formats (see section 5.3 Symbol Names), they can be specified with upper-case `B' and `F', as in `8B' and `9F'. A local label defined for the current position is written with a `H' appended to the number:

3H LDB $0,$1,2

This and traditional local-label formats cannot be mixed: a label must be defined and referred to using the same format.

There's a minor caveat: just as for the ordinary local symbols, the local symbols are translated into ordinary symbols using control characters are to hide the ordinal number of the symbol. Unfortunately, these symbols are not translated back in error messages. Thus you may see confusing error messages when local symbols are used. Control characters `\003' (control-C) and `\004' (control-D) are used for the MMIX-specific local-symbol syntax.

The symbol `Main' is handled specially; it is always global.

By defining the symbols `__.MMIX.start..text' and `__.MMIX.start..data', the address of respectively the `.text' and `.data' segments of the final program can be defined, though when linking more than one object file, the code or data in the object file containing the symbol is not guaranteed to be start at that position; just the final executable. See MMIX-loc.

8.21.3.3 Register names

Local and global registers are specified as `$0' to `$255'. The recognized special register names are `rJ', `rA', `rB', `rC', `rD', `rE', `rF', `rG', `rH', `rI', `rK', `rL', `rM', `rN', `rO', `rP', `rQ', `rR', `rS', `rT', `rU', `rV', `rW', `rX', `rY', `rZ', `rBB', `rTT', `rWW', `rXX', `rYY' and `rZZ'. A leading `:' is optional for special register names.

Local and global symbols can be equated to register names and used in place of ordinary registers.

Similarly for special registers, local and global symbols can be used. Also, symbols equated from numbers and constant expressions are allowed in place of a special register, except when either of the options --no-predefined-syms and --fixed-special-register-names are specified. Then only the special register names above are allowed for the instructions having a special register operand; GET and PUT.

8.21.3.4 Assembler Directives

LOC

The LOC directive sets the current location to the value of the operand field, which may include changing sections. If the operand is a constant, the section is set to either .data if the value is 0x2000000000000000 or larger, else it is set to .text. Within a section, the current location may only be changed to monotonically higher addresses. A LOC expression must be a previously defined symbol or a "pure" constant.

An example, which sets the label prev to the current location, and updates the current location to eight bytes forward:

prev LOC @+8

When a LOC has a constant as its operand, a symbol __.MMIX.start..text or __.MMIX.start..data is defined depending on the address as mentioned above. Each such symbol is interpreted as special by the linker, locating the section at that address. Note that if multiple files are linked, the first object file with that section will be mapped to that address (not necessarily the file with the LOC definition).

LOCAL

Example:

LOCAL external_symbol LOCAL 42 .local asymbol

This directive-operation generates a link-time assertion that the operand does not correspond to a global register. The operand is an expression that at link-time resolves to a register symbol or a number. A number is treated as the register having that number. There is one restriction on the use of this directive: the pseudo-directive must be placed in a section with contents, code or data.

IS

The IS directive:

asymbol IS an_expression

sets the symbol `asymbol' to `an_expression'. A symbol may not be set more than once using this directive. Local labels may be set using this directive, for example:

5H IS @+4

GREG

This directive reserves a global register, gives it an initial value and optionally gives it a symbolic name. Some examples:

areg GREG breg GREG data_value GREG data_buffer .greg creg, another_data_value

The symbolic register name can be used in place of a (non-special) register. If a value isn't provided, it defaults to zero. Unless the option `--no-merge-gregs' is specified, non-zero registers allocated with this directive may be eliminated by as; another register with the same value used in its place. Any of the instructions `CSWAP', `GO', `LDA', `LDBU', `LDB', `LDHT', `LDOU', `LDO', `LDSF', `LDTU', `LDT', `LDUNC', `LDVTS', `LDWU', `LDW', `PREGO', `PRELD', `PREST', `PUSHGO', `STBU', `STB', `STCO', `STHT', `STOU', `STSF', `STTU', `STT', `STUNC', `SYNCD', `SYNCID', can have a value nearby an initial value in place of its second and third operands. Here, "nearby" is defined as within the range 0...255 from the initial value of such an allocated register.

buffer1 BYTE 0,0,0,0,0 buffer2 BYTE 0,0,0,0,0 ... GREG buffer1 LDOU $42,buffer2

In the example above, the `Y' field of the LDOUI instruction (LDOU with a constant Z) will be replaced with the global register allocated for `buffer1', and the `Z' field will have the value 5, the offset from `buffer1' to `buffer2'. The result is equivalent to this code:

buffer1 BYTE 0,0,0,0,0 buffer2 BYTE 0,0,0,0,0 ... tmpreg GREG buffer1 LDOU $42,tmpreg,(buffer2-buffer1)

Global registers allocated with this directive are allocated in order higher-to-lower within a file. Other than that, the exact order of register allocation and elimination is undefined. For example, the order is undefined when more than one file with such directives are linked together. With the options `-x' and `--linker-allocated-gregs', `GREG' directives for two-operand cases like the one mentioned above can be omitted. Sufficient global registers will then be allocated by the linker.

BYTE

The `BYTE' directive takes a series of operands separated by a comma. If an operand is a string (see section 3.6.1.1 Strings), each character of that string is emitted as a byte. Other operands must be constant expressions without forward references, in the range 0...255. If you need operands having expressions with forward references, use `.byte' (see section 7.7 .byte expressions). An operand can be omitted, defaulting to a zero value.

WYDE

TETRA

OCTA

The directives `WYDE', `TETRA' and `OCTA' emit constants of two, four and eight bytes size respectively. Before anything else happens for the directive, the current location is aligned to the respective constant-size boundary. If a label is defined at the beginning of the line, its value will be that after the alignment. A single operand can be omitted, defaulting to a zero value emitted for the directive. Operands can be expressed as strings (see section 3.6.1.1 Strings), in which case each character in the string is emitted as a separate constant of the size indicated by the directive.

PREFIX

The `PREFIX' directive sets a symbol name prefix to be prepended to all symbols (except local symbols, see section 8.21.3.2 Symbols), that are not prefixed with `:', until the next `PREFIX' directive. Such prefixes accumulate. For example,

PREFIX a PREFIX b c IS 0

defines a symbol `abc' with the value 0.

BSPEC

ESPEC

A pair of `BSPEC' and `ESPEC' directives delimit a section of special contents (without specified semantics). Example:

BSPEC 42 TETRA 1,2,3 ESPEC

The single operand to `BSPEC' must be number in the range 0...255. The `BSPEC' number 80 is used by the GNU binutils implementation.